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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This header file contains identifiers and low-level driver functions (or macros) that can be used to access the device. </p>
<p>High-level driver functions are defined in <a class="el" href="xdpdma_8h.html" title="This file defines the functions implemented by the DPDMA driver present in the Zynq Ultrascale MP...">xdpdma.h</a></p>
<dl class="section note"><dt>Note</dt><dd>None.</dd></dl>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver     Who   Date     Changes
</p>
<hr/>
<p>
1.0  aad   04/12/16 Initial release.
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a05137b71ce7a978700ba5c362704a646"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a05137b71ce7a978700ba5c362704a646">XDpDma_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;XDpDma_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:a05137b71ce7a978700ba5c362704a646"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is a low-level function that reads from the specified register.  <a href="#a05137b71ce7a978700ba5c362704a646">More...</a><br/></td></tr>
<tr class="separator:a05137b71ce7a978700ba5c362704a646"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a836430cbab9cc5f0fae3b5f2b54daca6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a836430cbab9cc5f0fae3b5f2b54daca6">XDpDma_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;XDpDma_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="memdesc:a836430cbab9cc5f0fae3b5f2b54daca6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is a low-level function that writes to the specified register.  <a href="#a836430cbab9cc5f0fae3b5f2b54daca6">More...</a><br/></td></tr>
<tr class="separator:a836430cbab9cc5f0fae3b5f2b54daca6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6740ca444093c5883a293e6282d79ec7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a6740ca444093c5883a293e6282d79ec7">XDpDma_ReadModifyWrite</a>(BaseAddress, RegOffset, Data, Mask)</td></tr>
<tr class="memdesc:a6740ca444093c5883a293e6282d79ec7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is a low-level function that writes to the specified register.  <a href="#a6740ca444093c5883a293e6282d79ec7">More...</a><br/></td></tr>
<tr class="separator:a6740ca444093c5883a293e6282d79ec7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DPDMA registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Address mapping for the DPDMA. </p>
</div></td></tr>
<tr class="memitem:aefedc486b6de171b3a1f1a709c5d7d17"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aefedc486b6de171b3a1f1a709c5d7d17"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_BASEADDR</b>&#160;&#160;&#160;0XFD4C0000U</td></tr>
<tr class="separator:aefedc486b6de171b3a1f1a709c5d7d17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7e16e6689ff8b9c514eb8908baf79bc2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a7e16e6689ff8b9c514eb8908baf79bc2">XDPDMA_ERR_CTRL</a>&#160;&#160;&#160;0X0000</td></tr>
<tr class="memdesc:a7e16e6689ff8b9c514eb8908baf79bc2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_ERR_CTRL.  <a href="#a7e16e6689ff8b9c514eb8908baf79bc2">More...</a><br/></td></tr>
<tr class="separator:a7e16e6689ff8b9c514eb8908baf79bc2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a91b034bcce521925fb5b156496039efe"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a91b034bcce521925fb5b156496039efe"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ERR_CTRL_APB_ERR_RES_SHIFT</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:a91b034bcce521925fb5b156496039efe"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ERR_CTRL_APB_ERR_RES_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a5ab2e514792a77425488e3e335ac3bf3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a03ed9701bb0b3215ec2b511749d240b2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a03ed9701bb0b3215ec2b511749d240b2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ERR_CTRL_APB_ERR_RES_MASK</b>&#160;&#160;&#160;0X1</td></tr>
<tr class="separator:a03ed9701bb0b3215ec2b511749d240b2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ace9e0daf87e3d7d42ac516869d89d444"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ace9e0daf87e3d7d42ac516869d89d444">XDPDMA_ISR</a>&#160;&#160;&#160;0X0004U</td></tr>
<tr class="memdesc:ace9e0daf87e3d7d42ac516869d89d444"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_ISR.  <a href="#ace9e0daf87e3d7d42ac516869d89d444">More...</a><br/></td></tr>
<tr class="separator:ace9e0daf87e3d7d42ac516869d89d444"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a77a0e546d3be9c0c8bf9519e97babd74"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a77a0e546d3be9c0c8bf9519e97babd74"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_VSYNC_INT_SHIFT</b>&#160;&#160;&#160;27</td></tr>
<tr class="separator:a77a0e546d3be9c0c8bf9519e97babd74"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_VSYNC_INT_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a0a50cd54feaa0c8566505d79866530be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa3cf647e59ac6b10ae6f4fa1efd5c53d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa3cf647e59ac6b10ae6f4fa1efd5c53d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_VSYNC_INT_MASK</b>&#160;&#160;&#160;0X08000000U</td></tr>
<tr class="separator:aa3cf647e59ac6b10ae6f4fa1efd5c53d"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_AXI_RD_4K_CROSS_SHIFT</b>&#160;&#160;&#160;26</td></tr>
<tr class="separator:a3320c7ab7d90185e9e96137286b3273c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0e7fb11d4f0559adfa5a4e8e9b5a7d25"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0e7fb11d4f0559adfa5a4e8e9b5a7d25"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_AXI_RD_4K_CROSS_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a0e7fb11d4f0559adfa5a4e8e9b5a7d25"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_AXI_RD_4K_CROSS_MASK</b>&#160;&#160;&#160;0X04000000</td></tr>
<tr class="separator:a71df7d6011f1429100bf33b994ab617c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a523b6637baeab4384b29f4f59f3b2feb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a523b6637baeab4384b29f4f59f3b2feb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_WR_DATA_FIFO_FULL_SHIFT</b>&#160;&#160;&#160;25</td></tr>
<tr class="separator:a523b6637baeab4384b29f4f59f3b2feb"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_WR_DATA_FIFO_FULL_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a97046f33f9383fa58b84c80761ea99fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2f0bd8aa9f450b33df184e016da6797d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2f0bd8aa9f450b33df184e016da6797d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_WR_DATA_FIFO_FULL_MASK</b>&#160;&#160;&#160;0X02000000</td></tr>
<tr class="separator:a2f0bd8aa9f450b33df184e016da6797d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9c5d0396b42fbfd5db6bef7e46d4ff6d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9c5d0396b42fbfd5db6bef7e46d4ff6d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_WR_CMD_FIFO_FULL_SHIFT</b>&#160;&#160;&#160;24</td></tr>
<tr class="separator:a9c5d0396b42fbfd5db6bef7e46d4ff6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5d054f26f252c4a979c6ef596c450439"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5d054f26f252c4a979c6ef596c450439"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_WR_CMD_FIFO_FULL_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a5d054f26f252c4a979c6ef596c450439"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae47073f6acf80e79f49807234cf1b51c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae47073f6acf80e79f49807234cf1b51c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_WR_CMD_FIFO_FULL_MASK</b>&#160;&#160;&#160;0X01000000</td></tr>
<tr class="separator:ae47073f6acf80e79f49807234cf1b51c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad3ba0fbf07b95b95bd809725a413bb1d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad3ba0fbf07b95b95bd809725a413bb1d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR5_SHIFT</b>&#160;&#160;&#160;23</td></tr>
<tr class="separator:ad3ba0fbf07b95b95bd809725a413bb1d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a048e881275c89e6a224f2619c2c49323"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a048e881275c89e6a224f2619c2c49323"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a048e881275c89e6a224f2619c2c49323"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad5d85e35652f233a84f793569638baa9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad5d85e35652f233a84f793569638baa9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR5_MASK</b>&#160;&#160;&#160;0X800000</td></tr>
<tr class="separator:ad5d85e35652f233a84f793569638baa9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a07c22a95e55f5c05799607d4057af118"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a07c22a95e55f5c05799607d4057af118"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR4_SHIFT</b>&#160;&#160;&#160;22</td></tr>
<tr class="separator:a07c22a95e55f5c05799607d4057af118"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d6445cadc30f78841c6308f813e7e7c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9d6445cadc30f78841c6308f813e7e7c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a9d6445cadc30f78841c6308f813e7e7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adaccf3787c9aeadf02d1df19c92696fd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="adaccf3787c9aeadf02d1df19c92696fd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR4_MASK</b>&#160;&#160;&#160;0X400000</td></tr>
<tr class="separator:adaccf3787c9aeadf02d1df19c92696fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f12990007120f884019b1dc7d5f77e2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3f12990007120f884019b1dc7d5f77e2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR3_SHIFT</b>&#160;&#160;&#160;21</td></tr>
<tr class="separator:a3f12990007120f884019b1dc7d5f77e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d3c94e947245446b1b0fb36a480d19a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9d3c94e947245446b1b0fb36a480d19a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a9d3c94e947245446b1b0fb36a480d19a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a34ad42248751d14c8e487226c9280bf5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a34ad42248751d14c8e487226c9280bf5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR3_MASK</b>&#160;&#160;&#160;0X200000</td></tr>
<tr class="separator:a34ad42248751d14c8e487226c9280bf5"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR2_SHIFT</b>&#160;&#160;&#160;20</td></tr>
<tr class="separator:ac34e78492cdbed9211adef8bc116269b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acc3057922071e3800157025f8a4819ec"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acc3057922071e3800157025f8a4819ec"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:acc3057922071e3800157025f8a4819ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR2_MASK</b>&#160;&#160;&#160;0X100000</td></tr>
<tr class="separator:a0ec7a111a657544a1da622533bcedbee"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR1_SHIFT</b>&#160;&#160;&#160;19</td></tr>
<tr class="separator:a63df5887c7954ee36dec9e09b4e055c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a73a9ad559d6070aef9c7af6664d83f71"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR1_MASK</b>&#160;&#160;&#160;0X80000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR0_SHIFT</b>&#160;&#160;&#160;18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_ERR0_MASK</b>&#160;&#160;&#160;0X40000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR5_SHIFT</b>&#160;&#160;&#160;17</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR5_MASK</b>&#160;&#160;&#160;0X20000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR4_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR4_MASK</b>&#160;&#160;&#160;0X10000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR3_SHIFT</b>&#160;&#160;&#160;15</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR3_MASK</b>&#160;&#160;&#160;0X8000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR2_SHIFT</b>&#160;&#160;&#160;14</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR2_MASK</b>&#160;&#160;&#160;0X4000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR1_SHIFT</b>&#160;&#160;&#160;13</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR1_MASK</b>&#160;&#160;&#160;0X2000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR0_SHIFT</b>&#160;&#160;&#160;12</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DATA_AXI_ERR0_MASK</b>&#160;&#160;&#160;0X1000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN5_SHIFT</b>&#160;&#160;&#160;11</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN5_MASK</b>&#160;&#160;&#160;0X0800</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN4_SHIFT</b>&#160;&#160;&#160;10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN4_MASK</b>&#160;&#160;&#160;0X0400</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN3_SHIFT</b>&#160;&#160;&#160;9</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN3_MASK</b>&#160;&#160;&#160;0X0200</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN2_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN2_MASK</b>&#160;&#160;&#160;0X0100</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN1_SHIFT</b>&#160;&#160;&#160;7</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN1_MASK</b>&#160;&#160;&#160;0X80</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN0_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_NO_OSTAND_TRAN0_MASK</b>&#160;&#160;&#160;0X40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE5_SHIFT</b>&#160;&#160;&#160;5</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE5_MASK</b>&#160;&#160;&#160;0X20U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE4_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE4_MASK</b>&#160;&#160;&#160;0X10U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE3_SHIFT</b>&#160;&#160;&#160;3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE3_MASK</b>&#160;&#160;&#160;0X8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE2_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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<tr class="memitem:a562e70a6921f8e90c6c9dfa2f293a480"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a562e70a6921f8e90c6c9dfa2f293a480"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE2_MASK</b>&#160;&#160;&#160;0X4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE1_SHIFT</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a603ad642090991426dd0822350d0fe45"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a603ad642090991426dd0822350d0fe45"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE1_MASK</b>&#160;&#160;&#160;0X2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE0_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a6d280f69910a126d763f72c4437079ed"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6d280f69910a126d763f72c4437079ed"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ISR_DSCR_DONE0_MASK</b>&#160;&#160;&#160;0X1</td></tr>
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<tr class="memitem:a92d0fcfcd996d69e3ce0a2e70816f54a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a92d0fcfcd996d69e3ce0a2e70816f54a">XDPDMA_IMR</a>&#160;&#160;&#160;0X0008</td></tr>
<tr class="memdesc:a92d0fcfcd996d69e3ce0a2e70816f54a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_IMR.  <a href="#a92d0fcfcd996d69e3ce0a2e70816f54a">More...</a><br/></td></tr>
<tr class="separator:a92d0fcfcd996d69e3ce0a2e70816f54a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a158166fcedbc385b02167ce67195dcf9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a158166fcedbc385b02167ce67195dcf9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_VSYNC_INT_SHIFT</b>&#160;&#160;&#160;27</td></tr>
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<tr class="memitem:a7c67c1415dfd2a129a28e29f03faf4ee"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7c67c1415dfd2a129a28e29f03faf4ee"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_VSYNC_INT_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_VSYNC_INT_MASK</b>&#160;&#160;&#160;0X08000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_AXI_RD_4K_CROSS_SHIFT</b>&#160;&#160;&#160;26</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_AXI_RD_4K_CROSS_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_AXI_RD_4K_CROSS_MASK</b>&#160;&#160;&#160;0X04000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_WR_DATA_FIFO_FULL_SHIFT</b>&#160;&#160;&#160;25</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_WR_DATA_FIFO_FULL_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_WR_DATA_FIFO_FULL_MASK</b>&#160;&#160;&#160;0X02000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_WR_CMD_FIFO_FULL_SHIFT</b>&#160;&#160;&#160;24</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_WR_CMD_FIFO_FULL_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_WR_CMD_FIFO_FULL_MASK</b>&#160;&#160;&#160;0X01000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR5_SHIFT</b>&#160;&#160;&#160;23</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR5_MASK</b>&#160;&#160;&#160;0X800000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR4_SHIFT</b>&#160;&#160;&#160;22</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR4_MASK</b>&#160;&#160;&#160;0X400000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR3_SHIFT</b>&#160;&#160;&#160;21</td></tr>
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<tr class="memitem:a1cd026ee17e7e62daa4bb7bf81923fe9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1cd026ee17e7e62daa4bb7bf81923fe9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR3_MASK</b>&#160;&#160;&#160;0X200000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR2_SHIFT</b>&#160;&#160;&#160;20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a3fa855255361e62f461b8c95bc544a52"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3fa855255361e62f461b8c95bc544a52"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR2_MASK</b>&#160;&#160;&#160;0X100000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR1_SHIFT</b>&#160;&#160;&#160;19</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a69f716baddb3a9cb3e71fe7b2c80c299"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a69f716baddb3a9cb3e71fe7b2c80c299"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR1_MASK</b>&#160;&#160;&#160;0X80000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR0_SHIFT</b>&#160;&#160;&#160;18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a41ca3cb142d9bf6132e1e38473f358da"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a41ca3cb142d9bf6132e1e38473f358da"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_ERR0_MASK</b>&#160;&#160;&#160;0X40000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR5_SHIFT</b>&#160;&#160;&#160;17</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR5_MASK</b>&#160;&#160;&#160;0X20000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR4_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR4_MASK</b>&#160;&#160;&#160;0X10000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR3_SHIFT</b>&#160;&#160;&#160;15</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR3_MASK</b>&#160;&#160;&#160;0X8000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR2_SHIFT</b>&#160;&#160;&#160;14</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR2_MASK</b>&#160;&#160;&#160;0X4000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR1_SHIFT</b>&#160;&#160;&#160;13</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR1_MASK</b>&#160;&#160;&#160;0X2000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR0_SHIFT</b>&#160;&#160;&#160;12</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DATA_AXI_ERR0_MASK</b>&#160;&#160;&#160;0X1000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN5_SHIFT</b>&#160;&#160;&#160;11</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN5_MASK</b>&#160;&#160;&#160;0X0800</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN4_SHIFT</b>&#160;&#160;&#160;10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN4_MASK</b>&#160;&#160;&#160;0X0400</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN3_SHIFT</b>&#160;&#160;&#160;9</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN3_MASK</b>&#160;&#160;&#160;0X0200</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN2_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN2_MASK</b>&#160;&#160;&#160;0X0100</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN1_SHIFT</b>&#160;&#160;&#160;7</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN1_MASK</b>&#160;&#160;&#160;0X80</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN0_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_NO_OSTAND_TRAN0_MASK</b>&#160;&#160;&#160;0X40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE5_SHIFT</b>&#160;&#160;&#160;5</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE5_MASK</b>&#160;&#160;&#160;0X20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE4_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE4_MASK</b>&#160;&#160;&#160;0X10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE3_SHIFT</b>&#160;&#160;&#160;3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE3_MASK</b>&#160;&#160;&#160;0X8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE2_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE2_MASK</b>&#160;&#160;&#160;0X4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE1_SHIFT</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE1_MASK</b>&#160;&#160;&#160;0X2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE0_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IMR_DSCR_DONE0_MASK</b>&#160;&#160;&#160;0X1</td></tr>
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<tr class="memitem:a7bd98cc3f3b3d8929288e48f73f9fe6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a7bd98cc3f3b3d8929288e48f73f9fe6d">XDPDMA_IEN</a>&#160;&#160;&#160;0X000CU</td></tr>
<tr class="memdesc:a7bd98cc3f3b3d8929288e48f73f9fe6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_IEN.  <a href="#a7bd98cc3f3b3d8929288e48f73f9fe6d">More...</a><br/></td></tr>
<tr class="separator:a7bd98cc3f3b3d8929288e48f73f9fe6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_VSYNC_INT_SHIFT</b>&#160;&#160;&#160;27</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_VSYNC_INT_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_VSYNC_INT_MASK</b>&#160;&#160;&#160;0X08000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_AXI_RD_4K_CROSS_SHIFT</b>&#160;&#160;&#160;26</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_AXI_RD_4K_CROSS_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_AXI_RD_4K_CROSS_MASK</b>&#160;&#160;&#160;0X04000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_WR_DATA_FIFO_FULL_SHIFT</b>&#160;&#160;&#160;25</td></tr>
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<tr class="memitem:abd792d55e1d527a7a68d96ae710f59b7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abd792d55e1d527a7a68d96ae710f59b7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_WR_DATA_FIFO_FULL_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_WR_DATA_FIFO_FULL_MASK</b>&#160;&#160;&#160;0X02000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_WR_CMD_FIFO_FULL_SHIFT</b>&#160;&#160;&#160;24</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_WR_CMD_FIFO_FULL_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_WR_CMD_FIFO_FULL_MASK</b>&#160;&#160;&#160;0X01000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR5_SHIFT</b>&#160;&#160;&#160;23</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR5_MASK</b>&#160;&#160;&#160;0X800000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR4_SHIFT</b>&#160;&#160;&#160;22</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR4_MASK</b>&#160;&#160;&#160;0X400000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR3_SHIFT</b>&#160;&#160;&#160;21</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR3_MASK</b>&#160;&#160;&#160;0X200000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR2_SHIFT</b>&#160;&#160;&#160;20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR2_MASK</b>&#160;&#160;&#160;0X100000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR1_SHIFT</b>&#160;&#160;&#160;19</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR1_MASK</b>&#160;&#160;&#160;0X80000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR0_SHIFT</b>&#160;&#160;&#160;18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_ERR0_MASK</b>&#160;&#160;&#160;0X40000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR5_SHIFT</b>&#160;&#160;&#160;17</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR5_MASK</b>&#160;&#160;&#160;0X20000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR4_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR4_MASK</b>&#160;&#160;&#160;0X10000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR3_SHIFT</b>&#160;&#160;&#160;15</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR3_MASK</b>&#160;&#160;&#160;0X8000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR2_SHIFT</b>&#160;&#160;&#160;14</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR2_MASK</b>&#160;&#160;&#160;0X4000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR1_SHIFT</b>&#160;&#160;&#160;13</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR1_MASK</b>&#160;&#160;&#160;0X2000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR0_SHIFT</b>&#160;&#160;&#160;12</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DATA_AXI_ERR0_MASK</b>&#160;&#160;&#160;0X1000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN5_SHIFT</b>&#160;&#160;&#160;11</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN5_MASK</b>&#160;&#160;&#160;0X0800</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN4_SHIFT</b>&#160;&#160;&#160;10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN4_MASK</b>&#160;&#160;&#160;0X0400</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN3_SHIFT</b>&#160;&#160;&#160;9</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN3_MASK</b>&#160;&#160;&#160;0X0200</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN2_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN2_MASK</b>&#160;&#160;&#160;0X0100</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN1_SHIFT</b>&#160;&#160;&#160;7</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN1_MASK</b>&#160;&#160;&#160;0X80</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN0_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_NO_OSTAND_TRAN0_MASK</b>&#160;&#160;&#160;0X40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE5_SHIFT</b>&#160;&#160;&#160;5</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE5_MASK</b>&#160;&#160;&#160;0X20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE4_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE4_MASK</b>&#160;&#160;&#160;0X10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE3_SHIFT</b>&#160;&#160;&#160;3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE3_MASK</b>&#160;&#160;&#160;0X8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE2_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE2_MASK</b>&#160;&#160;&#160;0X4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE1_SHIFT</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE1_MASK</b>&#160;&#160;&#160;0X2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE0_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IEN_DSCR_DONE0_MASK</b>&#160;&#160;&#160;0X1</td></tr>
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<tr class="memitem:a2849f3b0fe6751abc24db3fea5796e4d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a2849f3b0fe6751abc24db3fea5796e4d">XDPDMA_IDS</a>&#160;&#160;&#160;0X0010</td></tr>
<tr class="memdesc:a2849f3b0fe6751abc24db3fea5796e4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_IDS.  <a href="#a2849f3b0fe6751abc24db3fea5796e4d">More...</a><br/></td></tr>
<tr class="separator:a2849f3b0fe6751abc24db3fea5796e4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3d53e75bd5d77a68dcde5c3614379979"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3d53e75bd5d77a68dcde5c3614379979"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_VSYNC_INT_SHIFT</b>&#160;&#160;&#160;27</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_VSYNC_INT_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_VSYNC_INT_MASK</b>&#160;&#160;&#160;0X08000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_AXI_RD_4K_CROSS_SHIFT</b>&#160;&#160;&#160;26</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_AXI_RD_4K_CROSS_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_AXI_RD_4K_CROSS_MASK</b>&#160;&#160;&#160;0X04000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_WR_DATA_FIFO_FULL_SHIFT</b>&#160;&#160;&#160;25</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_WR_DATA_FIFO_FULL_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_WR_DATA_FIFO_FULL_MASK</b>&#160;&#160;&#160;0X02000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_WR_CMD_FIFO_FULL_SHIFT</b>&#160;&#160;&#160;24</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_WR_CMD_FIFO_FULL_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_WR_CMD_FIFO_FULL_MASK</b>&#160;&#160;&#160;0X01000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR5_SHIFT</b>&#160;&#160;&#160;23</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR5_MASK</b>&#160;&#160;&#160;0X800000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR4_SHIFT</b>&#160;&#160;&#160;22</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR4_MASK</b>&#160;&#160;&#160;0X400000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR3_SHIFT</b>&#160;&#160;&#160;21</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR3_MASK</b>&#160;&#160;&#160;0X200000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR2_SHIFT</b>&#160;&#160;&#160;20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR2_MASK</b>&#160;&#160;&#160;0X100000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR1_SHIFT</b>&#160;&#160;&#160;19</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR1_MASK</b>&#160;&#160;&#160;0X80000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR0_SHIFT</b>&#160;&#160;&#160;18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_ERR0_MASK</b>&#160;&#160;&#160;0X40000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR5_SHIFT</b>&#160;&#160;&#160;17</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR5_MASK</b>&#160;&#160;&#160;0X20000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR4_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR4_MASK</b>&#160;&#160;&#160;0X10000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR3_SHIFT</b>&#160;&#160;&#160;15</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR3_MASK</b>&#160;&#160;&#160;0X8000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR2_SHIFT</b>&#160;&#160;&#160;14</td></tr>
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<tr class="memitem:a3193e755a9ec80e9e050520793260c5c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3193e755a9ec80e9e050520793260c5c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR2_MASK</b>&#160;&#160;&#160;0X4000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR1_SHIFT</b>&#160;&#160;&#160;13</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR1_MASK</b>&#160;&#160;&#160;0X2000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR0_SHIFT</b>&#160;&#160;&#160;12</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DATA_AXI_ERR0_MASK</b>&#160;&#160;&#160;0X1000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN5_SHIFT</b>&#160;&#160;&#160;11</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN5_MASK</b>&#160;&#160;&#160;0X0800</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN4_SHIFT</b>&#160;&#160;&#160;10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN4_MASK</b>&#160;&#160;&#160;0X0400</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN3_SHIFT</b>&#160;&#160;&#160;9</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN3_MASK</b>&#160;&#160;&#160;0X0200</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN2_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN2_MASK</b>&#160;&#160;&#160;0X0100</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN1_SHIFT</b>&#160;&#160;&#160;7</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN1_MASK</b>&#160;&#160;&#160;0X80</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN0_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_NO_OSTAND_TRAN0_MASK</b>&#160;&#160;&#160;0X40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE5_SHIFT</b>&#160;&#160;&#160;5</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE5_MASK</b>&#160;&#160;&#160;0X20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE4_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE4_MASK</b>&#160;&#160;&#160;0X10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE3_SHIFT</b>&#160;&#160;&#160;3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE3_MASK</b>&#160;&#160;&#160;0X8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE2_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a9715d97fb81f04bc468a2bb91ccb6d5e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9715d97fb81f04bc468a2bb91ccb6d5e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE2_MASK</b>&#160;&#160;&#160;0X4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE1_SHIFT</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE1_MASK</b>&#160;&#160;&#160;0X2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE0_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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<tr class="memitem:a58eb084ddde2a398bd6bb315f612ffc6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a58eb084ddde2a398bd6bb315f612ffc6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a2b41d1287bf00a3f4702f1eddfed35ef"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2b41d1287bf00a3f4702f1eddfed35ef"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_IDS_DSCR_DONE0_MASK</b>&#160;&#160;&#160;0X1</td></tr>
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<tr class="memitem:a4acf94c528731ceeede26f6d192d014c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a4acf94c528731ceeede26f6d192d014c">XDPDMA_EISR</a>&#160;&#160;&#160;0X0014</td></tr>
<tr class="memdesc:a4acf94c528731ceeede26f6d192d014c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_EISR.  <a href="#a4acf94c528731ceeede26f6d192d014c">More...</a><br/></td></tr>
<tr class="separator:a4acf94c528731ceeede26f6d192d014c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a2809d6666204b67529eb9a46fd35c7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7a2809d6666204b67529eb9a46fd35c7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_RD_CMD_FIFO_FULL_SHIFT</b>&#160;&#160;&#160;31</td></tr>
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<tr class="memitem:a7e0c9ea4fc47555a025e93c98b122fd9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7e0c9ea4fc47555a025e93c98b122fd9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_RD_CMD_FIFO_FULL_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_RD_CMD_FIFO_FULL_MASK</b>&#160;&#160;&#160;0X80000000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR5_SHIFT</b>&#160;&#160;&#160;30</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR5_MASK</b>&#160;&#160;&#160;0X40000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR4_SHIFT</b>&#160;&#160;&#160;29</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR4_MASK</b>&#160;&#160;&#160;0X20000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR3_SHIFT</b>&#160;&#160;&#160;28</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR3_MASK</b>&#160;&#160;&#160;0X10000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR2_SHIFT</b>&#160;&#160;&#160;27</td></tr>
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<tr class="memitem:ab2baeae7c65e8db727ba3accfc9a28c5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab2baeae7c65e8db727ba3accfc9a28c5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR2_MASK</b>&#160;&#160;&#160;0X08000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR1_SHIFT</b>&#160;&#160;&#160;26</td></tr>
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<tr class="memitem:a880744ce3781692aae092e2b3b9bac67"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a880744ce3781692aae092e2b3b9bac67"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR1_MASK</b>&#160;&#160;&#160;0X04000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR0_SHIFT</b>&#160;&#160;&#160;25</td></tr>
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<tr class="memitem:a58e8c4a20c19e010d8df2ebe5fc3b389"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a58e8c4a20c19e010d8df2ebe5fc3b389"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_DONE_ERR0_MASK</b>&#160;&#160;&#160;0X02000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR5_SHIFT</b>&#160;&#160;&#160;24</td></tr>
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<tr class="memitem:afd8b7bd020854a2677c7a37598371c26"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afd8b7bd020854a2677c7a37598371c26"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a1047a941e331ce3a4d0f6cfb89278bd0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1047a941e331ce3a4d0f6cfb89278bd0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR5_MASK</b>&#160;&#160;&#160;0X01000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR4_SHIFT</b>&#160;&#160;&#160;23</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR4_MASK</b>&#160;&#160;&#160;0X800000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR3_SHIFT</b>&#160;&#160;&#160;22</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR3_MASK</b>&#160;&#160;&#160;0X400000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR2_SHIFT</b>&#160;&#160;&#160;21</td></tr>
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<tr class="memitem:a7ee2838aec22433c5b5e6a497522fa74"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7ee2838aec22433c5b5e6a497522fa74"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR2_MASK</b>&#160;&#160;&#160;0X200000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR1_SHIFT</b>&#160;&#160;&#160;20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR1_MASK</b>&#160;&#160;&#160;0X100000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR0_SHIFT</b>&#160;&#160;&#160;19</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_WR_AXI_ERR0_MASK</b>&#160;&#160;&#160;0X80000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR5_SHIFT</b>&#160;&#160;&#160;18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR5_MASK</b>&#160;&#160;&#160;0X40000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR4_SHIFT</b>&#160;&#160;&#160;17</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR4_MASK</b>&#160;&#160;&#160;0X20000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR3_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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<tr class="memitem:a0009e8f8fc6741bde831a2a32bcb2126"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0009e8f8fc6741bde831a2a32bcb2126"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR3_MASK</b>&#160;&#160;&#160;0X10000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR2_SHIFT</b>&#160;&#160;&#160;15</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR2_MASK</b>&#160;&#160;&#160;0X8000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR1_SHIFT</b>&#160;&#160;&#160;14</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR1_MASK</b>&#160;&#160;&#160;0X4000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR0_SHIFT</b>&#160;&#160;&#160;13</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_CRC_ERR0_MASK</b>&#160;&#160;&#160;0X2000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR5_SHIFT</b>&#160;&#160;&#160;12</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR5_MASK</b>&#160;&#160;&#160;0X1000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR4_SHIFT</b>&#160;&#160;&#160;11</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR4_MASK</b>&#160;&#160;&#160;0X0800</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR3_SHIFT</b>&#160;&#160;&#160;10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR3_MASK</b>&#160;&#160;&#160;0X0400</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR2_SHIFT</b>&#160;&#160;&#160;9</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR2_MASK</b>&#160;&#160;&#160;0X0200</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR1_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR1_MASK</b>&#160;&#160;&#160;0X0100</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR0_SHIFT</b>&#160;&#160;&#160;7</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_PRE_ERR0_MASK</b>&#160;&#160;&#160;0X80</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR5_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR5_MASK</b>&#160;&#160;&#160;0X40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR4_SHIFT</b>&#160;&#160;&#160;5</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR4_MASK</b>&#160;&#160;&#160;0X20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR3_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR3_MASK</b>&#160;&#160;&#160;0X10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR2_SHIFT</b>&#160;&#160;&#160;3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR2_MASK</b>&#160;&#160;&#160;0X8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR1_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR1_MASK</b>&#160;&#160;&#160;0X4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR0_SHIFT</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a8f6e320a4e954856abf9d7ece6df290d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8f6e320a4e954856abf9d7ece6df290d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_DSCR_RD_AXI_ERR0_MASK</b>&#160;&#160;&#160;0X2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_INV_APB_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_INV_APB_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:aa9a49b2afb786609837086800dfab833"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa9a49b2afb786609837086800dfab833"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EISR_INV_APB_MASK</b>&#160;&#160;&#160;0X1</td></tr>
<tr class="separator:aa9a49b2afb786609837086800dfab833"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a584f0fe1ed788d81e9add223ae89ce3c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a584f0fe1ed788d81e9add223ae89ce3c">XDPDMA_EIMR</a>&#160;&#160;&#160;0X0018</td></tr>
<tr class="memdesc:a584f0fe1ed788d81e9add223ae89ce3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_EIMR.  <a href="#a584f0fe1ed788d81e9add223ae89ce3c">More...</a><br/></td></tr>
<tr class="separator:a584f0fe1ed788d81e9add223ae89ce3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab0ec25110a425fe5df6e587f5c3622c1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab0ec25110a425fe5df6e587f5c3622c1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_RD_CMD_FIFO_FULL_SHIFT</b>&#160;&#160;&#160;31</td></tr>
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<tr class="memitem:a8231546cc550ef1b8900111e4564452f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8231546cc550ef1b8900111e4564452f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_RD_CMD_FIFO_FULL_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a731c0392470abcbd37e72807c707b4a6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a731c0392470abcbd37e72807c707b4a6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_RD_CMD_FIFO_FULL_MASK</b>&#160;&#160;&#160;0X80000000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR5_SHIFT</b>&#160;&#160;&#160;30</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR5_MASK</b>&#160;&#160;&#160;0X40000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR4_SHIFT</b>&#160;&#160;&#160;29</td></tr>
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<tr class="memitem:a71a9265e3ad3aa457dc61a5ab3b6b727"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a71a9265e3ad3aa457dc61a5ab3b6b727"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR4_MASK</b>&#160;&#160;&#160;0X20000000</td></tr>
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<tr class="memitem:a2e317ae565d4506d9d7ec6e1132b1327"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2e317ae565d4506d9d7ec6e1132b1327"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR3_SHIFT</b>&#160;&#160;&#160;28</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR3_MASK</b>&#160;&#160;&#160;0X10000000</td></tr>
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<tr class="memitem:a3aa272ec33fbf3a5b9e499a9cb6a10dc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3aa272ec33fbf3a5b9e499a9cb6a10dc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR2_SHIFT</b>&#160;&#160;&#160;27</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR2_MASK</b>&#160;&#160;&#160;0X08000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR1_SHIFT</b>&#160;&#160;&#160;26</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR1_MASK</b>&#160;&#160;&#160;0X04000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR0_SHIFT</b>&#160;&#160;&#160;25</td></tr>
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<tr class="memitem:a391cc6df8ec7d2eb083397034ceb8f1f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a391cc6df8ec7d2eb083397034ceb8f1f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_DONE_ERR0_MASK</b>&#160;&#160;&#160;0X02000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR5_SHIFT</b>&#160;&#160;&#160;24</td></tr>
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<tr class="memitem:a4f9e222ca06abd823c310888ed178eb5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4f9e222ca06abd823c310888ed178eb5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:ac3d7d6451453cd40d745e27c847f1b42"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac3d7d6451453cd40d745e27c847f1b42"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR5_MASK</b>&#160;&#160;&#160;0X01000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR4_SHIFT</b>&#160;&#160;&#160;23</td></tr>
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<tr class="memitem:a41e80d83463f977a7bd4bc3f84c7cb66"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a41e80d83463f977a7bd4bc3f84c7cb66"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR4_MASK</b>&#160;&#160;&#160;0X800000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR3_SHIFT</b>&#160;&#160;&#160;22</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR3_MASK</b>&#160;&#160;&#160;0X400000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR2_SHIFT</b>&#160;&#160;&#160;21</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:aee9a40f88d4f18bfee4a5b08aee8127e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aee9a40f88d4f18bfee4a5b08aee8127e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR2_MASK</b>&#160;&#160;&#160;0X200000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR1_SHIFT</b>&#160;&#160;&#160;20</td></tr>
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<tr class="memitem:aa6753c456abde0d98dda07fcc980d601"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa6753c456abde0d98dda07fcc980d601"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a643713a4df9797bf6ad95a8fcd28fd9e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a643713a4df9797bf6ad95a8fcd28fd9e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR1_MASK</b>&#160;&#160;&#160;0X100000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR0_SHIFT</b>&#160;&#160;&#160;19</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_WR_AXI_ERR0_MASK</b>&#160;&#160;&#160;0X80000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR5_SHIFT</b>&#160;&#160;&#160;18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR5_MASK</b>&#160;&#160;&#160;0X40000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR4_SHIFT</b>&#160;&#160;&#160;17</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR4_MASK</b>&#160;&#160;&#160;0X20000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR3_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR3_MASK</b>&#160;&#160;&#160;0X10000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR2_SHIFT</b>&#160;&#160;&#160;15</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR2_MASK</b>&#160;&#160;&#160;0X8000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR1_SHIFT</b>&#160;&#160;&#160;14</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR1_MASK</b>&#160;&#160;&#160;0X4000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR0_SHIFT</b>&#160;&#160;&#160;13</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_CRC_ERR0_MASK</b>&#160;&#160;&#160;0X2000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR5_SHIFT</b>&#160;&#160;&#160;12</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR5_MASK</b>&#160;&#160;&#160;0X1000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR4_SHIFT</b>&#160;&#160;&#160;11</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR4_MASK</b>&#160;&#160;&#160;0X0800</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR3_SHIFT</b>&#160;&#160;&#160;10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR3_MASK</b>&#160;&#160;&#160;0X0400</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR2_SHIFT</b>&#160;&#160;&#160;9</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR2_MASK</b>&#160;&#160;&#160;0X0200</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR1_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR1_MASK</b>&#160;&#160;&#160;0X0100</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR0_SHIFT</b>&#160;&#160;&#160;7</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_PRE_ERR0_MASK</b>&#160;&#160;&#160;0X80</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR5_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR5_MASK</b>&#160;&#160;&#160;0X40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR4_SHIFT</b>&#160;&#160;&#160;5</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR4_MASK</b>&#160;&#160;&#160;0X20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR3_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR3_MASK</b>&#160;&#160;&#160;0X10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR2_SHIFT</b>&#160;&#160;&#160;3</td></tr>
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<tr class="memitem:a4b401f37ecfab852fb26c0303d7fe312"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4b401f37ecfab852fb26c0303d7fe312"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:ae8f5c3a895b6953af978a3fbeb0f8b53"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae8f5c3a895b6953af978a3fbeb0f8b53"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR2_MASK</b>&#160;&#160;&#160;0X8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR1_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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<tr class="memitem:a3d9d4e86016d500ff8d407c010c4ce68"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3d9d4e86016d500ff8d407c010c4ce68"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR1_MASK</b>&#160;&#160;&#160;0X4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR0_SHIFT</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_DSCR_RD_AXI_ERR0_MASK</b>&#160;&#160;&#160;0X2</td></tr>
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<tr class="memitem:a333359a8e627e421b365a2b87b59a52c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a333359a8e627e421b365a2b87b59a52c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_INV_APB_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_INV_APB_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a1bc394198f2e97b566910d0866226bf0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1bc394198f2e97b566910d0866226bf0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIMR_INV_APB_MASK</b>&#160;&#160;&#160;0X1</td></tr>
<tr class="separator:a1bc394198f2e97b566910d0866226bf0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac74c27e37b98e661231ed17c7346cb91"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ac74c27e37b98e661231ed17c7346cb91">XDPDMA_EIEN</a>&#160;&#160;&#160;0X001C</td></tr>
<tr class="memdesc:ac74c27e37b98e661231ed17c7346cb91"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_EIEN.  <a href="#ac74c27e37b98e661231ed17c7346cb91">More...</a><br/></td></tr>
<tr class="separator:ac74c27e37b98e661231ed17c7346cb91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae0f2e28eecf17da323841bf8cab6072b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae0f2e28eecf17da323841bf8cab6072b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_RD_CMD_FIFO_FULL_SHIFT</b>&#160;&#160;&#160;31</td></tr>
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<tr class="memitem:a3d3581d5d05357a3d193f3266384f40f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3d3581d5d05357a3d193f3266384f40f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_RD_CMD_FIFO_FULL_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_RD_CMD_FIFO_FULL_MASK</b>&#160;&#160;&#160;0X80000000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR5_SHIFT</b>&#160;&#160;&#160;30</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR5_MASK</b>&#160;&#160;&#160;0X40000000</td></tr>
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<tr class="memitem:a396d409a13954af5c2dac2e78dedb0e8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a396d409a13954af5c2dac2e78dedb0e8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR4_SHIFT</b>&#160;&#160;&#160;29</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR4_MASK</b>&#160;&#160;&#160;0X20000000</td></tr>
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<tr class="memitem:a000a7a501a6c15922898a28c2e15c361"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a000a7a501a6c15922898a28c2e15c361"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR3_SHIFT</b>&#160;&#160;&#160;28</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a43a45a4f3d7698d6008ae3c49146d87b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a43a45a4f3d7698d6008ae3c49146d87b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR3_MASK</b>&#160;&#160;&#160;0X10000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR2_SHIFT</b>&#160;&#160;&#160;27</td></tr>
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<tr class="memitem:a448244c00a7796ef869373608ab9a867"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a448244c00a7796ef869373608ab9a867"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a1f8398e615967e40a20dee2611ea5abd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1f8398e615967e40a20dee2611ea5abd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR2_MASK</b>&#160;&#160;&#160;0X08000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR1_SHIFT</b>&#160;&#160;&#160;26</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a45b2838ea2ff08266351eb244e910e24"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a45b2838ea2ff08266351eb244e910e24"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR1_MASK</b>&#160;&#160;&#160;0X04000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR0_SHIFT</b>&#160;&#160;&#160;25</td></tr>
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<tr class="memitem:aa41b160062815bd4c2c23cbb90cc99c8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa41b160062815bd4c2c23cbb90cc99c8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_DONE_ERR0_MASK</b>&#160;&#160;&#160;0X02000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR5_SHIFT</b>&#160;&#160;&#160;24</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:ab40b85e08b110b44fbccf43e5c04c3a6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab40b85e08b110b44fbccf43e5c04c3a6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR5_MASK</b>&#160;&#160;&#160;0X01000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR4_SHIFT</b>&#160;&#160;&#160;23</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR4_MASK</b>&#160;&#160;&#160;0X800000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR3_SHIFT</b>&#160;&#160;&#160;22</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR3_MASK</b>&#160;&#160;&#160;0X400000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR2_SHIFT</b>&#160;&#160;&#160;21</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR2_MASK</b>&#160;&#160;&#160;0X200000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR1_SHIFT</b>&#160;&#160;&#160;20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR1_MASK</b>&#160;&#160;&#160;0X100000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR0_SHIFT</b>&#160;&#160;&#160;19</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_WR_AXI_ERR0_MASK</b>&#160;&#160;&#160;0X80000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR5_SHIFT</b>&#160;&#160;&#160;18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR5_MASK</b>&#160;&#160;&#160;0X40000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR4_SHIFT</b>&#160;&#160;&#160;17</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR4_MASK</b>&#160;&#160;&#160;0X20000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR3_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR3_MASK</b>&#160;&#160;&#160;0X10000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR2_SHIFT</b>&#160;&#160;&#160;15</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR2_MASK</b>&#160;&#160;&#160;0X8000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR1_SHIFT</b>&#160;&#160;&#160;14</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR1_MASK</b>&#160;&#160;&#160;0X4000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR0_SHIFT</b>&#160;&#160;&#160;13</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_CRC_ERR0_MASK</b>&#160;&#160;&#160;0X2000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR5_SHIFT</b>&#160;&#160;&#160;12</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR5_MASK</b>&#160;&#160;&#160;0X1000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR4_SHIFT</b>&#160;&#160;&#160;11</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR4_MASK</b>&#160;&#160;&#160;0X0800</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR3_SHIFT</b>&#160;&#160;&#160;10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR3_MASK</b>&#160;&#160;&#160;0X0400</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR2_SHIFT</b>&#160;&#160;&#160;9</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR2_MASK</b>&#160;&#160;&#160;0X0200</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR1_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR1_MASK</b>&#160;&#160;&#160;0X0100</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR0_SHIFT</b>&#160;&#160;&#160;7</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_PRE_ERR0_MASK</b>&#160;&#160;&#160;0X80</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR5_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR5_MASK</b>&#160;&#160;&#160;0X40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR4_SHIFT</b>&#160;&#160;&#160;5</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR4_MASK</b>&#160;&#160;&#160;0X20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR3_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR3_MASK</b>&#160;&#160;&#160;0X10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR2_SHIFT</b>&#160;&#160;&#160;3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR2_MASK</b>&#160;&#160;&#160;0X8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR1_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR1_MASK</b>&#160;&#160;&#160;0X4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR0_SHIFT</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a876a0328bad26a587b1c02a7e64529a6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a876a0328bad26a587b1c02a7e64529a6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_DSCR_RD_AXI_ERR0_MASK</b>&#160;&#160;&#160;0X2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_INV_APB_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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<tr class="memitem:a774b0481be4c07a05ada8f2a97677720"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a774b0481be4c07a05ada8f2a97677720"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_INV_APB_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a223f2d742c0e283e5f6614f609e1cd66"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a223f2d742c0e283e5f6614f609e1cd66"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIEN_INV_APB_MASK</b>&#160;&#160;&#160;0X1</td></tr>
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<tr class="memitem:add4abc05f7be2300a456fdfb4e86f109"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#add4abc05f7be2300a456fdfb4e86f109">XDPDMA_EIDS</a>&#160;&#160;&#160;0X0020</td></tr>
<tr class="memdesc:add4abc05f7be2300a456fdfb4e86f109"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_EIDS.  <a href="#add4abc05f7be2300a456fdfb4e86f109">More...</a><br/></td></tr>
<tr class="separator:add4abc05f7be2300a456fdfb4e86f109"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a75d623450583c61f893d1ceca891e478"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a75d623450583c61f893d1ceca891e478"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_RD_CMD_FIFO_FULL_SHIFT</b>&#160;&#160;&#160;31</td></tr>
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<tr class="memitem:a3f636a72a4ef3d9834391e7fe1be5922"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3f636a72a4ef3d9834391e7fe1be5922"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_RD_CMD_FIFO_FULL_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_RD_CMD_FIFO_FULL_MASK</b>&#160;&#160;&#160;0X80000000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR5_SHIFT</b>&#160;&#160;&#160;30</td></tr>
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<tr class="memitem:acb0a527ed59093bcd0d787ba33b0edeb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acb0a527ed59093bcd0d787ba33b0edeb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR5_MASK</b>&#160;&#160;&#160;0X40000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR4_SHIFT</b>&#160;&#160;&#160;29</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR4_MASK</b>&#160;&#160;&#160;0X20000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR3_SHIFT</b>&#160;&#160;&#160;28</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR3_MASK</b>&#160;&#160;&#160;0X10000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR2_SHIFT</b>&#160;&#160;&#160;27</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a1acc2b1e4dfb051d7f9455d96a0ce7e2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1acc2b1e4dfb051d7f9455d96a0ce7e2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR2_MASK</b>&#160;&#160;&#160;0X08000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR1_SHIFT</b>&#160;&#160;&#160;26</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a38a0c061271aed7ded8e4c863078e613"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a38a0c061271aed7ded8e4c863078e613"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR1_MASK</b>&#160;&#160;&#160;0X04000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR0_SHIFT</b>&#160;&#160;&#160;25</td></tr>
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<tr class="memitem:a94f2b7423e33dad8a58cc2eb967bcec9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a94f2b7423e33dad8a58cc2eb967bcec9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_DONE_ERR0_MASK</b>&#160;&#160;&#160;0X02000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR5_SHIFT</b>&#160;&#160;&#160;24</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR5_MASK</b>&#160;&#160;&#160;0X01000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR4_SHIFT</b>&#160;&#160;&#160;23</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR4_MASK</b>&#160;&#160;&#160;0X800000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR3_SHIFT</b>&#160;&#160;&#160;22</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR3_MASK</b>&#160;&#160;&#160;0X400000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR2_SHIFT</b>&#160;&#160;&#160;21</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR2_MASK</b>&#160;&#160;&#160;0X200000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR1_SHIFT</b>&#160;&#160;&#160;20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR1_MASK</b>&#160;&#160;&#160;0X100000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR0_SHIFT</b>&#160;&#160;&#160;19</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_WR_AXI_ERR0_MASK</b>&#160;&#160;&#160;0X80000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR5_SHIFT</b>&#160;&#160;&#160;18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR5_MASK</b>&#160;&#160;&#160;0X40000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR4_SHIFT</b>&#160;&#160;&#160;17</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR4_MASK</b>&#160;&#160;&#160;0X20000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR3_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR3_MASK</b>&#160;&#160;&#160;0X10000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR2_SHIFT</b>&#160;&#160;&#160;15</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR2_MASK</b>&#160;&#160;&#160;0X8000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR1_SHIFT</b>&#160;&#160;&#160;14</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR1_MASK</b>&#160;&#160;&#160;0X4000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR0_SHIFT</b>&#160;&#160;&#160;13</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_CRC_ERR0_MASK</b>&#160;&#160;&#160;0X2000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR5_SHIFT</b>&#160;&#160;&#160;12</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR5_MASK</b>&#160;&#160;&#160;0X1000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR4_SHIFT</b>&#160;&#160;&#160;11</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR4_MASK</b>&#160;&#160;&#160;0X0800</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR3_SHIFT</b>&#160;&#160;&#160;10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR3_MASK</b>&#160;&#160;&#160;0X0400</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR2_SHIFT</b>&#160;&#160;&#160;9</td></tr>
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<tr class="memitem:a2e9c8203b4fd9a6253e218184decacdb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2e9c8203b4fd9a6253e218184decacdb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR2_MASK</b>&#160;&#160;&#160;0X0200</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR1_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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<tr class="memitem:acdd60f0a53180f5a48a16c3b3f4d80f9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acdd60f0a53180f5a48a16c3b3f4d80f9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR1_MASK</b>&#160;&#160;&#160;0X0100</td></tr>
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<tr class="memitem:ab989b13ff1ac769484bef0993bdc80ab"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab989b13ff1ac769484bef0993bdc80ab"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR0_SHIFT</b>&#160;&#160;&#160;7</td></tr>
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<tr class="memitem:af4343a002e77951f4bab5799f22eca31"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af4343a002e77951f4bab5799f22eca31"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:af2030b8e81397c349bb96631ca4590d9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af2030b8e81397c349bb96631ca4590d9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_PRE_ERR0_MASK</b>&#160;&#160;&#160;0X80</td></tr>
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<tr class="memitem:a2878bc1be568f874154b3ff7f990bfec"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2878bc1be568f874154b3ff7f990bfec"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR5_SHIFT</b>&#160;&#160;&#160;6</td></tr>
<tr class="separator:a2878bc1be568f874154b3ff7f990bfec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7c9b0f614b960ae0d91cfdcc137f6efd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7c9b0f614b960ae0d91cfdcc137f6efd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:ae1a2fda11481dbbc3550eb1a93ed621e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae1a2fda11481dbbc3550eb1a93ed621e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR5_MASK</b>&#160;&#160;&#160;0X40</td></tr>
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<tr class="memitem:ad1af79368d1a21bdf1367b75efd2a719"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad1af79368d1a21bdf1367b75efd2a719"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR4_SHIFT</b>&#160;&#160;&#160;5</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a1c7ea325f76d5c4fe67834ba4d08a0e0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1c7ea325f76d5c4fe67834ba4d08a0e0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR4_MASK</b>&#160;&#160;&#160;0X20</td></tr>
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<tr class="memitem:a2a6b3e5ee46d12f5b54ef2f1900f5cb7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2a6b3e5ee46d12f5b54ef2f1900f5cb7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR3_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a9a56c3b585e3696436cda0ed03bc118c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9a56c3b585e3696436cda0ed03bc118c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR3_MASK</b>&#160;&#160;&#160;0X10</td></tr>
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<tr class="memitem:aba37868cb6bdc546c171700452336603"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aba37868cb6bdc546c171700452336603"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR2_SHIFT</b>&#160;&#160;&#160;3</td></tr>
<tr class="separator:aba37868cb6bdc546c171700452336603"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acee1b59ed5888eaad6a38df4982d8d32"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acee1b59ed5888eaad6a38df4982d8d32"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a31557d048183b2afb0dfc161be96b77f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a31557d048183b2afb0dfc161be96b77f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR2_MASK</b>&#160;&#160;&#160;0X8</td></tr>
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<tr class="memitem:aba0a2b07ca8334defa8a7a9a0bdd8966"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aba0a2b07ca8334defa8a7a9a0bdd8966"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR1_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR1_MASK</b>&#160;&#160;&#160;0X4</td></tr>
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<tr class="memitem:a450e27ce6fe9e00702a9bc60d11ef80e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a450e27ce6fe9e00702a9bc60d11ef80e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR0_SHIFT</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a4267f73e35c94b7a3c1c411caa9c452c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4267f73e35c94b7a3c1c411caa9c452c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_DSCR_RD_AXI_ERR0_MASK</b>&#160;&#160;&#160;0X2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_INV_APB_SHIFT</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:abc627eb33a70968231a7030995054d35"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab9f281a1874b6aa06fe7e23705dbc0b9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab9f281a1874b6aa06fe7e23705dbc0b9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_INV_APB_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:ab9f281a1874b6aa06fe7e23705dbc0b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afc19f60fb99fc4e0ed35e42f06c41b33"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afc19f60fb99fc4e0ed35e42f06c41b33"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_EIDS_INV_APB_MASK</b>&#160;&#160;&#160;0X1</td></tr>
<tr class="separator:afc19f60fb99fc4e0ed35e42f06c41b33"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8ef7259c3e780171f2e405484ee4fec3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a8ef7259c3e780171f2e405484ee4fec3">XDPDMA_CNTL</a>&#160;&#160;&#160;0X0100</td></tr>
<tr class="memdesc:a8ef7259c3e780171f2e405484ee4fec3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CNTL.  <a href="#a8ef7259c3e780171f2e405484ee4fec3">More...</a><br/></td></tr>
<tr class="separator:a8ef7259c3e780171f2e405484ee4fec3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acd9b1930d59d62b2de10bcebfe383b5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#acd9b1930d59d62b2de10bcebfe383b5e">XDPDMA_GBL</a>&#160;&#160;&#160;0X0104U</td></tr>
<tr class="memdesc:acd9b1930d59d62b2de10bcebfe383b5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_GBL.  <a href="#acd9b1930d59d62b2de10bcebfe383b5e">More...</a><br/></td></tr>
<tr class="separator:acd9b1930d59d62b2de10bcebfe383b5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4faf96730749a023a47d540e6b86d858"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4faf96730749a023a47d540e6b86d858"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH5_SHIFT</b>&#160;&#160;&#160;11</td></tr>
<tr class="separator:a4faf96730749a023a47d540e6b86d858"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab4e3744c95c9a70e807039f46451aa98"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab4e3744c95c9a70e807039f46451aa98"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:ab4e3744c95c9a70e807039f46451aa98"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa8cf3d0d332b72816fcc03d785dad3de"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa8cf3d0d332b72816fcc03d785dad3de"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH5_MASK</b>&#160;&#160;&#160;0X0800</td></tr>
<tr class="separator:aa8cf3d0d332b72816fcc03d785dad3de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4df1a8305244c5563410595671e947e9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4df1a8305244c5563410595671e947e9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH4_SHIFT</b>&#160;&#160;&#160;10</td></tr>
<tr class="separator:a4df1a8305244c5563410595671e947e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a55305ac24fb6d6fb8b840d7ecbb0e109"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a55305ac24fb6d6fb8b840d7ecbb0e109"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a55305ac24fb6d6fb8b840d7ecbb0e109"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab29892608f83d428c00522cdac785a37"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab29892608f83d428c00522cdac785a37"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH4_MASK</b>&#160;&#160;&#160;0X0400</td></tr>
<tr class="separator:ab29892608f83d428c00522cdac785a37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a95085e0b13c1b1a28ca8e0ce3ef36eaa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a95085e0b13c1b1a28ca8e0ce3ef36eaa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH3_SHIFT</b>&#160;&#160;&#160;9</td></tr>
<tr class="separator:a95085e0b13c1b1a28ca8e0ce3ef36eaa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a26d065ee8fd93b8eb2f4035c1c635439"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a26d065ee8fd93b8eb2f4035c1c635439"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a26d065ee8fd93b8eb2f4035c1c635439"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab3e27787c3c59a9500be288f8c821a80"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab3e27787c3c59a9500be288f8c821a80"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH3_MASK</b>&#160;&#160;&#160;0X0200</td></tr>
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<tr class="memitem:a972b33fbef8e6c04241d36ad58fd03ab"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a972b33fbef8e6c04241d36ad58fd03ab"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH2_SHIFT</b>&#160;&#160;&#160;8</td></tr>
<tr class="separator:a972b33fbef8e6c04241d36ad58fd03ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac552fea6e9ac955ebe7e10c042474bc1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac552fea6e9ac955ebe7e10c042474bc1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:ac552fea6e9ac955ebe7e10c042474bc1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa94e09621f3eef93660e426e14ee4bdd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa94e09621f3eef93660e426e14ee4bdd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH2_MASK</b>&#160;&#160;&#160;0X0100</td></tr>
<tr class="separator:aa94e09621f3eef93660e426e14ee4bdd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d874e52b9d36e310875cda0f73eba14"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9d874e52b9d36e310875cda0f73eba14"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH1_SHIFT</b>&#160;&#160;&#160;7</td></tr>
<tr class="separator:a9d874e52b9d36e310875cda0f73eba14"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a426c08c1b2cbb28e64077db777d658a8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a426c08c1b2cbb28e64077db777d658a8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a4c17fba6164e85f2a5103361bd10ec65"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4c17fba6164e85f2a5103361bd10ec65"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH1_MASK</b>&#160;&#160;&#160;0X80</td></tr>
<tr class="separator:a4c17fba6164e85f2a5103361bd10ec65"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a230e4d10b2b5e0df5a25afe76ca4c9fa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a230e4d10b2b5e0df5a25afe76ca4c9fa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH0_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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<tr class="memitem:a1dd8104e452cd6dae3a804a320903e68"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1dd8104e452cd6dae3a804a320903e68"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a1dd8104e452cd6dae3a804a320903e68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a56c1abbfa52c2d22ed336772dbf3cdf5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a56c1abbfa52c2d22ed336772dbf3cdf5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_RTRG_CH0_MASK</b>&#160;&#160;&#160;0X40U</td></tr>
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<tr class="memitem:ad665e88b2764ec2c9a26a1d7683f9a30"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad665e88b2764ec2c9a26a1d7683f9a30"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH5_SHIFT</b>&#160;&#160;&#160;5</td></tr>
<tr class="separator:ad665e88b2764ec2c9a26a1d7683f9a30"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad5958de760cc81c5af1724f057b955be"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad5958de760cc81c5af1724f057b955be"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH5_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:ad5958de760cc81c5af1724f057b955be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a170cde7715d860ecf9bad23cea21478a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a170cde7715d860ecf9bad23cea21478a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH5_MASK</b>&#160;&#160;&#160;0X20</td></tr>
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<tr class="memitem:a34639d35c3424508eea22be3966e43ab"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a34639d35c3424508eea22be3966e43ab"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH4_SHIFT</b>&#160;&#160;&#160;4</td></tr>
<tr class="separator:a34639d35c3424508eea22be3966e43ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae5f1ba35e5f499138ada9bc40bc4d0c6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae5f1ba35e5f499138ada9bc40bc4d0c6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH4_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:ae5f1ba35e5f499138ada9bc40bc4d0c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a56507d65cb211805224b0e34c52ede7f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a56507d65cb211805224b0e34c52ede7f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH4_MASK</b>&#160;&#160;&#160;0X10</td></tr>
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<tr class="memitem:a1bb06957874991f938d13745548cc2b4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1bb06957874991f938d13745548cc2b4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH3_SHIFT</b>&#160;&#160;&#160;3</td></tr>
<tr class="separator:a1bb06957874991f938d13745548cc2b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9adf23ae464429a02743259543826eb1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9adf23ae464429a02743259543826eb1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH3_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a9adf23ae464429a02743259543826eb1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a52937f6e319ca8703ce0dc46a7668c97"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a52937f6e319ca8703ce0dc46a7668c97"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH3_MASK</b>&#160;&#160;&#160;0X8</td></tr>
<tr class="separator:a52937f6e319ca8703ce0dc46a7668c97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab026d488674f982181fe232a35eff118"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab026d488674f982181fe232a35eff118"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH2_SHIFT</b>&#160;&#160;&#160;2</td></tr>
<tr class="separator:ab026d488674f982181fe232a35eff118"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a44c33af53d30a265635ff8ca5e64af93"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a44c33af53d30a265635ff8ca5e64af93"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH2_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a44c33af53d30a265635ff8ca5e64af93"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a944fea34bb2744a85bbf9f4c9c33c679"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a944fea34bb2744a85bbf9f4c9c33c679"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH2_MASK</b>&#160;&#160;&#160;0X4</td></tr>
<tr class="separator:a944fea34bb2744a85bbf9f4c9c33c679"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae9ec9d9783b98a734f65584312cec4f0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae9ec9d9783b98a734f65584312cec4f0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH1_SHIFT</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:ae9ec9d9783b98a734f65584312cec4f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a26573ba66323be214f7ce20571653e02"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a26573ba66323be214f7ce20571653e02"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH1_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:a26573ba66323be214f7ce20571653e02"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a98ecbcc850b1628fb1c42d99ff7121aa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a98ecbcc850b1628fb1c42d99ff7121aa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH1_MASK</b>&#160;&#160;&#160;0X2</td></tr>
<tr class="separator:a98ecbcc850b1628fb1c42d99ff7121aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a01d2e3336210f83573e8196b1be3459e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a01d2e3336210f83573e8196b1be3459e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH0_SHIFT</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:a01d2e3336210f83573e8196b1be3459e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adbc6d0cacfb9022bd8101f588a978074"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="adbc6d0cacfb9022bd8101f588a978074"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH0_WIDTH</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:adbc6d0cacfb9022bd8101f588a978074"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5b7c3c3da2faf739b56badebc35e37f5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5b7c3c3da2faf739b56badebc35e37f5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_GBL_TRG_CH0_MASK</b>&#160;&#160;&#160;0X1U</td></tr>
<tr class="separator:a5b7c3c3da2faf739b56badebc35e37f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a991f6234e0556e6e723eb66f35a6f082"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a991f6234e0556e6e723eb66f35a6f082">XDPDMA_CH0_DSCR_STRT_ADDRE</a>&#160;&#160;&#160;0X0200U</td></tr>
<tr class="memdesc:a991f6234e0556e6e723eb66f35a6f082"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH0_DSCR_STRT_ADDRE.  <a href="#a991f6234e0556e6e723eb66f35a6f082">More...</a><br/></td></tr>
<tr class="separator:a991f6234e0556e6e723eb66f35a6f082"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abd78f71b01f8530af95fb64f69d876ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#abd78f71b01f8530af95fb64f69d876ea">XDPDMA_CH0_DSCR_STRT_ADDR</a>&#160;&#160;&#160;0X0204U</td></tr>
<tr class="memdesc:abd78f71b01f8530af95fb64f69d876ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH0_DSCR_STRT_ADDR.  <a href="#abd78f71b01f8530af95fb64f69d876ea">More...</a><br/></td></tr>
<tr class="separator:abd78f71b01f8530af95fb64f69d876ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adcc6ad043d68513eb376091718cafafe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#adcc6ad043d68513eb376091718cafafe">XDPDMA_CH0_DSCR_NEXT_ADDRE</a>&#160;&#160;&#160;0X0208</td></tr>
<tr class="memdesc:adcc6ad043d68513eb376091718cafafe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH0_DSCR_NEXT_ADDRE.  <a href="#adcc6ad043d68513eb376091718cafafe">More...</a><br/></td></tr>
<tr class="separator:adcc6ad043d68513eb376091718cafafe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afc59a959d6b0550dcdc267e735f33cb6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#afc59a959d6b0550dcdc267e735f33cb6">XDPDMA_CH0_DSCR_NEXT_ADDR</a>&#160;&#160;&#160;0X020C</td></tr>
<tr class="memdesc:afc59a959d6b0550dcdc267e735f33cb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH0_DSCR_NEXT_ADDR.  <a href="#afc59a959d6b0550dcdc267e735f33cb6">More...</a><br/></td></tr>
<tr class="separator:afc59a959d6b0550dcdc267e735f33cb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae4f4baee2a66dc28a10f8f83a5dfd861"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ae4f4baee2a66dc28a10f8f83a5dfd861">XDPDMA_CH0_PYLD_CUR_ADDRE</a>&#160;&#160;&#160;0X0210</td></tr>
<tr class="memdesc:ae4f4baee2a66dc28a10f8f83a5dfd861"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH0_PYLD_CUR_ADDRE.  <a href="#ae4f4baee2a66dc28a10f8f83a5dfd861">More...</a><br/></td></tr>
<tr class="separator:ae4f4baee2a66dc28a10f8f83a5dfd861"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a07c70571b263fbff92b84d1ecb98f1bf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a07c70571b263fbff92b84d1ecb98f1bf">XDPDMA_CH0_PYLD_CUR_ADDR</a>&#160;&#160;&#160;0X0214</td></tr>
<tr class="memdesc:a07c70571b263fbff92b84d1ecb98f1bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH0_PYLD_CUR_ADDR.  <a href="#a07c70571b263fbff92b84d1ecb98f1bf">More...</a><br/></td></tr>
<tr class="separator:a07c70571b263fbff92b84d1ecb98f1bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a92edcf2bfb1c790b8168ebdca1297987"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a92edcf2bfb1c790b8168ebdca1297987">XDPDMA_CH0_CNTL</a>&#160;&#160;&#160;0X0218U</td></tr>
<tr class="memdesc:a92edcf2bfb1c790b8168ebdca1297987"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH0_CNTL.  <a href="#a92edcf2bfb1c790b8168ebdca1297987">More...</a><br/></td></tr>
<tr class="separator:a92edcf2bfb1c790b8168ebdca1297987"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acb1ee5a115aa9315ba86a68b7582f257"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acb1ee5a115aa9315ba86a68b7582f257"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CNTL_QOS_VIDEO</b>&#160;&#160;&#160;0x11</td></tr>
<tr class="separator:acb1ee5a115aa9315ba86a68b7582f257"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a83f42b898372fe67e0bb5d7919cdcac6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a83f42b898372fe67e0bb5d7919cdcac6">XDPDMA_CH0_STATUS</a>&#160;&#160;&#160;0X021CU</td></tr>
<tr class="memdesc:a83f42b898372fe67e0bb5d7919cdcac6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH0_STATUS.  <a href="#a83f42b898372fe67e0bb5d7919cdcac6">More...</a><br/></td></tr>
<tr class="separator:a83f42b898372fe67e0bb5d7919cdcac6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae09303aba43f8418f295f0ff4dd34f92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ae09303aba43f8418f295f0ff4dd34f92">XDPDMA_CH0_VDO</a>&#160;&#160;&#160;0X0220</td></tr>
<tr class="memdesc:ae09303aba43f8418f295f0ff4dd34f92"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH0_VDO.  <a href="#ae09303aba43f8418f295f0ff4dd34f92">More...</a><br/></td></tr>
<tr class="separator:ae09303aba43f8418f295f0ff4dd34f92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a468a7a272cfb638c4e439a93329aca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a1a468a7a272cfb638c4e439a93329aca">XDPDMA_CH0_PYLD_SZ</a>&#160;&#160;&#160;0X0224</td></tr>
<tr class="memdesc:a1a468a7a272cfb638c4e439a93329aca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH0_PYLD_SZ.  <a href="#a1a468a7a272cfb638c4e439a93329aca">More...</a><br/></td></tr>
<tr class="separator:a1a468a7a272cfb638c4e439a93329aca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a09b2ae341d14ddfa549e8ab3834c3196"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a09b2ae341d14ddfa549e8ab3834c3196">XDPDMA_CH0_DSCR_ID</a>&#160;&#160;&#160;0X0228</td></tr>
<tr class="memdesc:a09b2ae341d14ddfa549e8ab3834c3196"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH0_DSCR_ID.  <a href="#a09b2ae341d14ddfa549e8ab3834c3196">More...</a><br/></td></tr>
<tr class="separator:a09b2ae341d14ddfa549e8ab3834c3196"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a838a5495033542c257ca35b82c2aa477"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a838a5495033542c257ca35b82c2aa477">XDPDMA_CH1_DSCR_STRT_ADDRE</a>&#160;&#160;&#160;0X0300</td></tr>
<tr class="memdesc:a838a5495033542c257ca35b82c2aa477"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH1_DSCR_STRT_ADDRE.  <a href="#a838a5495033542c257ca35b82c2aa477">More...</a><br/></td></tr>
<tr class="separator:a838a5495033542c257ca35b82c2aa477"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6fa9a18f33a9772a8a580933d7b03a73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a6fa9a18f33a9772a8a580933d7b03a73">XDPDMA_CH1_DSCR_STRT_ADDR</a>&#160;&#160;&#160;0X0304</td></tr>
<tr class="memdesc:a6fa9a18f33a9772a8a580933d7b03a73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH1_DSCR_STRT_ADDR.  <a href="#a6fa9a18f33a9772a8a580933d7b03a73">More...</a><br/></td></tr>
<tr class="separator:a6fa9a18f33a9772a8a580933d7b03a73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0b06d219911219117b2395959ebb8ba0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a0b06d219911219117b2395959ebb8ba0">XDPDMA_CH1_DSCR_NEXT_ADDRE</a>&#160;&#160;&#160;0X0308</td></tr>
<tr class="memdesc:a0b06d219911219117b2395959ebb8ba0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH1_DSCR_NEXT_ADDRE.  <a href="#a0b06d219911219117b2395959ebb8ba0">More...</a><br/></td></tr>
<tr class="separator:a0b06d219911219117b2395959ebb8ba0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae8e52410cadfe52524a23147ec6c1b44"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ae8e52410cadfe52524a23147ec6c1b44">XDPDMA_CH1_DSCR_NEXT_ADDR</a>&#160;&#160;&#160;0X030C</td></tr>
<tr class="memdesc:ae8e52410cadfe52524a23147ec6c1b44"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH1_DSCR_NEXT_ADDR.  <a href="#ae8e52410cadfe52524a23147ec6c1b44">More...</a><br/></td></tr>
<tr class="separator:ae8e52410cadfe52524a23147ec6c1b44"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aabab7a547102c88990ed3d99aa8b80e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#aabab7a547102c88990ed3d99aa8b80e9">XDPDMA_CH1_PYLD_CUR_ADDRE</a>&#160;&#160;&#160;0X0310</td></tr>
<tr class="memdesc:aabab7a547102c88990ed3d99aa8b80e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH1_PYLD_CUR_ADDRE.  <a href="#aabab7a547102c88990ed3d99aa8b80e9">More...</a><br/></td></tr>
<tr class="separator:aabab7a547102c88990ed3d99aa8b80e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa3c7d69760787868b85d2d8f75a44243"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#aa3c7d69760787868b85d2d8f75a44243">XDPDMA_CH1_PYLD_CUR_ADDR</a>&#160;&#160;&#160;0X0314</td></tr>
<tr class="memdesc:aa3c7d69760787868b85d2d8f75a44243"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH1_PYLD_CUR_ADDR.  <a href="#aa3c7d69760787868b85d2d8f75a44243">More...</a><br/></td></tr>
<tr class="separator:aa3c7d69760787868b85d2d8f75a44243"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adf0241f99ad07d09a66557be911d0975"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#adf0241f99ad07d09a66557be911d0975">XDPDMA_CH1_CNTL</a>&#160;&#160;&#160;0X0318</td></tr>
<tr class="memdesc:adf0241f99ad07d09a66557be911d0975"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH1_CNTL.  <a href="#adf0241f99ad07d09a66557be911d0975">More...</a><br/></td></tr>
<tr class="separator:adf0241f99ad07d09a66557be911d0975"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a54adbe2e6805c17f5e7d1b5cc15692a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a54adbe2e6805c17f5e7d1b5cc15692a7">XDPDMA_CH1_STATUS</a>&#160;&#160;&#160;0X031C</td></tr>
<tr class="memdesc:a54adbe2e6805c17f5e7d1b5cc15692a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH1_STATUS.  <a href="#a54adbe2e6805c17f5e7d1b5cc15692a7">More...</a><br/></td></tr>
<tr class="separator:a54adbe2e6805c17f5e7d1b5cc15692a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af24fb66e7b209f835184289ae36ee36a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#af24fb66e7b209f835184289ae36ee36a">XDPDMA_CH1_VDO</a>&#160;&#160;&#160;0X0320</td></tr>
<tr class="memdesc:af24fb66e7b209f835184289ae36ee36a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH1_VDO.  <a href="#af24fb66e7b209f835184289ae36ee36a">More...</a><br/></td></tr>
<tr class="separator:af24fb66e7b209f835184289ae36ee36a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a180f50f97fb4e14435b35fe63d61ac64"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a180f50f97fb4e14435b35fe63d61ac64">XDPDMA_CH1_PYLD_SZ</a>&#160;&#160;&#160;0X0324</td></tr>
<tr class="memdesc:a180f50f97fb4e14435b35fe63d61ac64"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH1_PYLD_SZ.  <a href="#a180f50f97fb4e14435b35fe63d61ac64">More...</a><br/></td></tr>
<tr class="separator:a180f50f97fb4e14435b35fe63d61ac64"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a51be3073d3032a7ae655e3e588785a15"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a51be3073d3032a7ae655e3e588785a15">XDPDMA_CH1_DSCR_ID</a>&#160;&#160;&#160;0X0328</td></tr>
<tr class="memdesc:a51be3073d3032a7ae655e3e588785a15"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH1_DSCR_ID.  <a href="#a51be3073d3032a7ae655e3e588785a15">More...</a><br/></td></tr>
<tr class="separator:a51be3073d3032a7ae655e3e588785a15"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a07c328da361c190edfe49c699a295779"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a07c328da361c190edfe49c699a295779">XDPDMA_CH2_DSCR_STRT_ADDRE</a>&#160;&#160;&#160;0X0400</td></tr>
<tr class="memdesc:a07c328da361c190edfe49c699a295779"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH2_DSCR_STRT_ADDRE.  <a href="#a07c328da361c190edfe49c699a295779">More...</a><br/></td></tr>
<tr class="separator:a07c328da361c190edfe49c699a295779"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1e9c5e509ee56fd597ca21f83e7594cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a1e9c5e509ee56fd597ca21f83e7594cd">XDPDMA_CH2_DSCR_STRT_ADDR</a>&#160;&#160;&#160;0X0404</td></tr>
<tr class="memdesc:a1e9c5e509ee56fd597ca21f83e7594cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH2_DSCR_STRT_ADDR.  <a href="#a1e9c5e509ee56fd597ca21f83e7594cd">More...</a><br/></td></tr>
<tr class="separator:a1e9c5e509ee56fd597ca21f83e7594cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a27cba17fb4ca046bccf321dcaed13738"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a27cba17fb4ca046bccf321dcaed13738">XDPDMA_CH2_DSCR_NEXT_ADDRE</a>&#160;&#160;&#160;0X0408</td></tr>
<tr class="memdesc:a27cba17fb4ca046bccf321dcaed13738"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH2_DSCR_NEXT_ADDRE.  <a href="#a27cba17fb4ca046bccf321dcaed13738">More...</a><br/></td></tr>
<tr class="separator:a27cba17fb4ca046bccf321dcaed13738"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a24eeab5d6028cf73cf27ce4e1a32406b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a24eeab5d6028cf73cf27ce4e1a32406b">XDPDMA_CH2_DSCR_NEXT_ADDR</a>&#160;&#160;&#160;0X040C</td></tr>
<tr class="memdesc:a24eeab5d6028cf73cf27ce4e1a32406b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH2_DSCR_NEXT_ADDR.  <a href="#a24eeab5d6028cf73cf27ce4e1a32406b">More...</a><br/></td></tr>
<tr class="separator:a24eeab5d6028cf73cf27ce4e1a32406b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7930ea87af739ba87dcec63e2a5069f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a7930ea87af739ba87dcec63e2a5069f4">XDPDMA_CH2_PYLD_CUR_ADDRE</a>&#160;&#160;&#160;0X0410</td></tr>
<tr class="memdesc:a7930ea87af739ba87dcec63e2a5069f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH2_PYLD_CUR_ADDRE.  <a href="#a7930ea87af739ba87dcec63e2a5069f4">More...</a><br/></td></tr>
<tr class="separator:a7930ea87af739ba87dcec63e2a5069f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9c43476d38eee3524660904391b7301e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a9c43476d38eee3524660904391b7301e">XDPDMA_CH2_PYLD_CUR_ADDR</a>&#160;&#160;&#160;0X0414</td></tr>
<tr class="memdesc:a9c43476d38eee3524660904391b7301e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH2_PYLD_CUR_ADDR.  <a href="#a9c43476d38eee3524660904391b7301e">More...</a><br/></td></tr>
<tr class="separator:a9c43476d38eee3524660904391b7301e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad79048ee00c1ac857520a93996e260a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ad79048ee00c1ac857520a93996e260a8">XDPDMA_CH2_CNTL</a>&#160;&#160;&#160;0X0418</td></tr>
<tr class="memdesc:ad79048ee00c1ac857520a93996e260a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH2_CNTL.  <a href="#ad79048ee00c1ac857520a93996e260a8">More...</a><br/></td></tr>
<tr class="separator:ad79048ee00c1ac857520a93996e260a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a174208187f3bd59b987baed4aebaa88e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a174208187f3bd59b987baed4aebaa88e">XDPDMA_CH2_STATUS</a>&#160;&#160;&#160;0X041C</td></tr>
<tr class="memdesc:a174208187f3bd59b987baed4aebaa88e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH2_STATUS.  <a href="#a174208187f3bd59b987baed4aebaa88e">More...</a><br/></td></tr>
<tr class="separator:a174208187f3bd59b987baed4aebaa88e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2420134029f56c26ff3c8f84adf39fd3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a2420134029f56c26ff3c8f84adf39fd3">XDPDMA_CH2_VDO</a>&#160;&#160;&#160;0X0420</td></tr>
<tr class="memdesc:a2420134029f56c26ff3c8f84adf39fd3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH2_VDO.  <a href="#a2420134029f56c26ff3c8f84adf39fd3">More...</a><br/></td></tr>
<tr class="separator:a2420134029f56c26ff3c8f84adf39fd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9464a8b39bf0218f962263d8d8165a12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a9464a8b39bf0218f962263d8d8165a12">XDPDMA_CH2_PYLD_SZ</a>&#160;&#160;&#160;0X0424</td></tr>
<tr class="memdesc:a9464a8b39bf0218f962263d8d8165a12"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH2_PYLD_SZ.  <a href="#a9464a8b39bf0218f962263d8d8165a12">More...</a><br/></td></tr>
<tr class="separator:a9464a8b39bf0218f962263d8d8165a12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3424199190b4c20992d7a3683262d6ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a3424199190b4c20992d7a3683262d6ba">XDPDMA_CH2_DSCR_ID</a>&#160;&#160;&#160;0X0428</td></tr>
<tr class="memdesc:a3424199190b4c20992d7a3683262d6ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH2_DSCR_ID.  <a href="#a3424199190b4c20992d7a3683262d6ba">More...</a><br/></td></tr>
<tr class="separator:a3424199190b4c20992d7a3683262d6ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a899cf6d0537238921a4feb690a9f2f69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a899cf6d0537238921a4feb690a9f2f69">XDPDMA_CH3_DSCR_STRT_ADDRE</a>&#160;&#160;&#160;0X0500</td></tr>
<tr class="memdesc:a899cf6d0537238921a4feb690a9f2f69"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH3_DSCR_STRT_ADDRE.  <a href="#a899cf6d0537238921a4feb690a9f2f69">More...</a><br/></td></tr>
<tr class="separator:a899cf6d0537238921a4feb690a9f2f69"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6de8f7d3387d33d28355c72232dfb2f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a6de8f7d3387d33d28355c72232dfb2f2">XDPDMA_CH3_DSCR_STRT_ADDR</a>&#160;&#160;&#160;0X0504</td></tr>
<tr class="memdesc:a6de8f7d3387d33d28355c72232dfb2f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH3_DSCR_STRT_ADDR.  <a href="#a6de8f7d3387d33d28355c72232dfb2f2">More...</a><br/></td></tr>
<tr class="separator:a6de8f7d3387d33d28355c72232dfb2f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74a3b5246ce91732eec1cdd303fec4d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a74a3b5246ce91732eec1cdd303fec4d9">XDPDMA_CH3_DSCR_NEXT_ADDRE</a>&#160;&#160;&#160;0X0508</td></tr>
<tr class="memdesc:a74a3b5246ce91732eec1cdd303fec4d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH3_DSCR_NEXT_ADDRE.  <a href="#a74a3b5246ce91732eec1cdd303fec4d9">More...</a><br/></td></tr>
<tr class="separator:a74a3b5246ce91732eec1cdd303fec4d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a977cdb3d4313659354009810f7277a62"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a977cdb3d4313659354009810f7277a62">XDPDMA_CH3_DSCR_NEXT_ADDR</a>&#160;&#160;&#160;0X050C</td></tr>
<tr class="memdesc:a977cdb3d4313659354009810f7277a62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH3_DSCR_NEXT_ADDR.  <a href="#a977cdb3d4313659354009810f7277a62">More...</a><br/></td></tr>
<tr class="separator:a977cdb3d4313659354009810f7277a62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa57ee9cb549632fcc9ab768ba58e6121"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#aa57ee9cb549632fcc9ab768ba58e6121">XDPDMA_CH3_PYLD_CUR_ADDRE</a>&#160;&#160;&#160;0X0510</td></tr>
<tr class="memdesc:aa57ee9cb549632fcc9ab768ba58e6121"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH3_PYLD_CUR_ADDRE.  <a href="#aa57ee9cb549632fcc9ab768ba58e6121">More...</a><br/></td></tr>
<tr class="separator:aa57ee9cb549632fcc9ab768ba58e6121"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a49ae885b83aabf0eb3d6e49e1be1904e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a49ae885b83aabf0eb3d6e49e1be1904e">XDPDMA_CH3_PYLD_CUR_ADDR</a>&#160;&#160;&#160;0X0514</td></tr>
<tr class="memdesc:a49ae885b83aabf0eb3d6e49e1be1904e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH3_PYLD_CUR_ADDR.  <a href="#a49ae885b83aabf0eb3d6e49e1be1904e">More...</a><br/></td></tr>
<tr class="separator:a49ae885b83aabf0eb3d6e49e1be1904e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0f51ff98221cebff1c2b490c072bb61f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a0f51ff98221cebff1c2b490c072bb61f">XDPDMA_CH3_CNTL</a>&#160;&#160;&#160;0X0518</td></tr>
<tr class="memdesc:a0f51ff98221cebff1c2b490c072bb61f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH3_CNTL.  <a href="#a0f51ff98221cebff1c2b490c072bb61f">More...</a><br/></td></tr>
<tr class="separator:a0f51ff98221cebff1c2b490c072bb61f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a28e9952949e1b86e1fe64b480221ba8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a28e9952949e1b86e1fe64b480221ba8b">XDPDMA_CH3_STATUS</a>&#160;&#160;&#160;0X051C</td></tr>
<tr class="memdesc:a28e9952949e1b86e1fe64b480221ba8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH3_STATUS.  <a href="#a28e9952949e1b86e1fe64b480221ba8b">More...</a><br/></td></tr>
<tr class="separator:a28e9952949e1b86e1fe64b480221ba8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab0639641282a93a5614e6d1c2c0d932a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ab0639641282a93a5614e6d1c2c0d932a">XDPDMA_CH3_VDO</a>&#160;&#160;&#160;0X0520</td></tr>
<tr class="memdesc:ab0639641282a93a5614e6d1c2c0d932a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH3_VDO.  <a href="#ab0639641282a93a5614e6d1c2c0d932a">More...</a><br/></td></tr>
<tr class="separator:ab0639641282a93a5614e6d1c2c0d932a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2054066aaea2ba768171aa54d7c715d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a2054066aaea2ba768171aa54d7c715d9">XDPDMA_CH3_PYLD_SZ</a>&#160;&#160;&#160;0X0524</td></tr>
<tr class="memdesc:a2054066aaea2ba768171aa54d7c715d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH3_PYLD_SZ.  <a href="#a2054066aaea2ba768171aa54d7c715d9">More...</a><br/></td></tr>
<tr class="separator:a2054066aaea2ba768171aa54d7c715d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa89a23e17f5dca705dd19bd809734c1c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#aa89a23e17f5dca705dd19bd809734c1c">XDPDMA_CH3_DSCR_ID</a>&#160;&#160;&#160;0X0528</td></tr>
<tr class="memdesc:aa89a23e17f5dca705dd19bd809734c1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH3_DSCR_ID.  <a href="#aa89a23e17f5dca705dd19bd809734c1c">More...</a><br/></td></tr>
<tr class="separator:aa89a23e17f5dca705dd19bd809734c1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a66b3c1a5524bea5746e3710f785a25c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a66b3c1a5524bea5746e3710f785a25c2">XDPDMA_CH4_DSCR_STRT_ADDRE</a>&#160;&#160;&#160;0X0600</td></tr>
<tr class="memdesc:a66b3c1a5524bea5746e3710f785a25c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH4_DSCR_STRT_ADDRE.  <a href="#a66b3c1a5524bea5746e3710f785a25c2">More...</a><br/></td></tr>
<tr class="separator:a66b3c1a5524bea5746e3710f785a25c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad443ff9b10e6977908eaa2634c9aa538"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ad443ff9b10e6977908eaa2634c9aa538">XDPDMA_CH4_DSCR_STRT_ADDR</a>&#160;&#160;&#160;0X0604</td></tr>
<tr class="memdesc:ad443ff9b10e6977908eaa2634c9aa538"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH4_DSCR_STRT_ADDR.  <a href="#ad443ff9b10e6977908eaa2634c9aa538">More...</a><br/></td></tr>
<tr class="separator:ad443ff9b10e6977908eaa2634c9aa538"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abb7642899e2f3020e8b1e16c96ca7ceb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#abb7642899e2f3020e8b1e16c96ca7ceb">XDPDMA_CH4_DSCR_NEXT_ADDRE</a>&#160;&#160;&#160;0X0608</td></tr>
<tr class="memdesc:abb7642899e2f3020e8b1e16c96ca7ceb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH4_DSCR_NEXT_ADDRE.  <a href="#abb7642899e2f3020e8b1e16c96ca7ceb">More...</a><br/></td></tr>
<tr class="separator:abb7642899e2f3020e8b1e16c96ca7ceb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4930f1be4260d774052c6436e24d6d64"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a4930f1be4260d774052c6436e24d6d64">XDPDMA_CH4_DSCR_NEXT_ADDR</a>&#160;&#160;&#160;0X060C</td></tr>
<tr class="memdesc:a4930f1be4260d774052c6436e24d6d64"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH4_DSCR_NEXT_ADDR.  <a href="#a4930f1be4260d774052c6436e24d6d64">More...</a><br/></td></tr>
<tr class="separator:a4930f1be4260d774052c6436e24d6d64"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae98fd97a3b1ca8c2ccd0cbe4d2abae17"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ae98fd97a3b1ca8c2ccd0cbe4d2abae17">XDPDMA_CH4_PYLD_CUR_ADDRE</a>&#160;&#160;&#160;0X0610</td></tr>
<tr class="memdesc:ae98fd97a3b1ca8c2ccd0cbe4d2abae17"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH4_PYLD_CUR_ADDRE.  <a href="#ae98fd97a3b1ca8c2ccd0cbe4d2abae17">More...</a><br/></td></tr>
<tr class="separator:ae98fd97a3b1ca8c2ccd0cbe4d2abae17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad60588b1e6b47e841dd36dae71978a07"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ad60588b1e6b47e841dd36dae71978a07">XDPDMA_CH4_PYLD_CUR_ADDR</a>&#160;&#160;&#160;0X0614</td></tr>
<tr class="memdesc:ad60588b1e6b47e841dd36dae71978a07"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH4_PYLD_CUR_ADDR.  <a href="#ad60588b1e6b47e841dd36dae71978a07">More...</a><br/></td></tr>
<tr class="separator:ad60588b1e6b47e841dd36dae71978a07"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a477f10fb1961935108d8cc9d13483209"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a477f10fb1961935108d8cc9d13483209">XDPDMA_CH4_CNTL</a>&#160;&#160;&#160;0X0618</td></tr>
<tr class="memdesc:a477f10fb1961935108d8cc9d13483209"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH4_CNTL.  <a href="#a477f10fb1961935108d8cc9d13483209">More...</a><br/></td></tr>
<tr class="separator:a477f10fb1961935108d8cc9d13483209"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afda009aaa74723d26c6ad2ca57f2028c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#afda009aaa74723d26c6ad2ca57f2028c">XDPDMA_CH4_STATUS</a>&#160;&#160;&#160;0X061C</td></tr>
<tr class="memdesc:afda009aaa74723d26c6ad2ca57f2028c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH4_STATUS.  <a href="#afda009aaa74723d26c6ad2ca57f2028c">More...</a><br/></td></tr>
<tr class="separator:afda009aaa74723d26c6ad2ca57f2028c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a755b2d11cabc3a67143464e5ba68854b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a755b2d11cabc3a67143464e5ba68854b">XDPDMA_CH4_VDO</a>&#160;&#160;&#160;0X0620</td></tr>
<tr class="memdesc:a755b2d11cabc3a67143464e5ba68854b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH4_VDO.  <a href="#a755b2d11cabc3a67143464e5ba68854b">More...</a><br/></td></tr>
<tr class="separator:a755b2d11cabc3a67143464e5ba68854b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a184c60737fe7e22521b4e1ab74aed5e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a184c60737fe7e22521b4e1ab74aed5e6">XDPDMA_CH4_PYLD_SZ</a>&#160;&#160;&#160;0X0624</td></tr>
<tr class="memdesc:a184c60737fe7e22521b4e1ab74aed5e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH4_PYLD_SZ.  <a href="#a184c60737fe7e22521b4e1ab74aed5e6">More...</a><br/></td></tr>
<tr class="separator:a184c60737fe7e22521b4e1ab74aed5e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7423c58a9102a77da3934aa0bd599660"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a7423c58a9102a77da3934aa0bd599660">XDPDMA_CH4_DSCR_ID</a>&#160;&#160;&#160;0X0628</td></tr>
<tr class="memdesc:a7423c58a9102a77da3934aa0bd599660"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH4_DSCR_ID.  <a href="#a7423c58a9102a77da3934aa0bd599660">More...</a><br/></td></tr>
<tr class="separator:a7423c58a9102a77da3934aa0bd599660"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4c5206b6dce1a65a1e6db4114621c5fc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a4c5206b6dce1a65a1e6db4114621c5fc">XDPDMA_CH5_DSCR_STRT_ADDRE</a>&#160;&#160;&#160;0X0700</td></tr>
<tr class="memdesc:a4c5206b6dce1a65a1e6db4114621c5fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH5_DSCR_STRT_ADDRE.  <a href="#a4c5206b6dce1a65a1e6db4114621c5fc">More...</a><br/></td></tr>
<tr class="separator:a4c5206b6dce1a65a1e6db4114621c5fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af9597e4aec3ced8b5e3a6d45485ee861"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#af9597e4aec3ced8b5e3a6d45485ee861">XDPDMA_CH5_DSCR_STRT_ADDR</a>&#160;&#160;&#160;0X0704</td></tr>
<tr class="memdesc:af9597e4aec3ced8b5e3a6d45485ee861"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH5_DSCR_STRT_ADDR.  <a href="#af9597e4aec3ced8b5e3a6d45485ee861">More...</a><br/></td></tr>
<tr class="separator:af9597e4aec3ced8b5e3a6d45485ee861"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a42f34bdc393cf3492f578c5d996263"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a1a42f34bdc393cf3492f578c5d996263">XDPDMA_CH5_DSCR_NEXT_ADDRE</a>&#160;&#160;&#160;0X0708</td></tr>
<tr class="memdesc:a1a42f34bdc393cf3492f578c5d996263"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH5_DSCR_NEXT_ADDRE.  <a href="#a1a42f34bdc393cf3492f578c5d996263">More...</a><br/></td></tr>
<tr class="separator:a1a42f34bdc393cf3492f578c5d996263"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab779b463c7a0e3acb425deff37219a17"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ab779b463c7a0e3acb425deff37219a17">XDPDMA_CH5_DSCR_NEXT_ADDR</a>&#160;&#160;&#160;0X070C</td></tr>
<tr class="memdesc:ab779b463c7a0e3acb425deff37219a17"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH5_DSCR_NEXT_ADDR.  <a href="#ab779b463c7a0e3acb425deff37219a17">More...</a><br/></td></tr>
<tr class="separator:ab779b463c7a0e3acb425deff37219a17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aadf8c4c53a62f5cc7c39f353d3ca1e0a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#aadf8c4c53a62f5cc7c39f353d3ca1e0a">XDPDMA_CH5_PYLD_CUR_ADDRE</a>&#160;&#160;&#160;0X0710</td></tr>
<tr class="memdesc:aadf8c4c53a62f5cc7c39f353d3ca1e0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH5_PYLD_CUR_ADDRE.  <a href="#aadf8c4c53a62f5cc7c39f353d3ca1e0a">More...</a><br/></td></tr>
<tr class="separator:aadf8c4c53a62f5cc7c39f353d3ca1e0a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a397cac23ead0877eb96b859078d88ab0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a397cac23ead0877eb96b859078d88ab0">XDPDMA_CH5_PYLD_CUR_ADDR</a>&#160;&#160;&#160;0X0714</td></tr>
<tr class="memdesc:a397cac23ead0877eb96b859078d88ab0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH5_PYLD_CUR_ADDR.  <a href="#a397cac23ead0877eb96b859078d88ab0">More...</a><br/></td></tr>
<tr class="separator:a397cac23ead0877eb96b859078d88ab0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8a40bc00f2c620de3dc434bebaf4e1ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a8a40bc00f2c620de3dc434bebaf4e1ed">XDPDMA_CH5_CNTL</a>&#160;&#160;&#160;0X0718</td></tr>
<tr class="memdesc:a8a40bc00f2c620de3dc434bebaf4e1ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH5_CNTL.  <a href="#a8a40bc00f2c620de3dc434bebaf4e1ed">More...</a><br/></td></tr>
<tr class="separator:a8a40bc00f2c620de3dc434bebaf4e1ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab76a5988722598d68ab200d4e0c1b940"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ab76a5988722598d68ab200d4e0c1b940">XDPDMA_CH5_STATUS</a>&#160;&#160;&#160;0X071C</td></tr>
<tr class="memdesc:ab76a5988722598d68ab200d4e0c1b940"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH5_STATUS.  <a href="#ab76a5988722598d68ab200d4e0c1b940">More...</a><br/></td></tr>
<tr class="separator:ab76a5988722598d68ab200d4e0c1b940"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6725b830ddf92c80bb4edbe8cd3342c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a6725b830ddf92c80bb4edbe8cd3342c6">XDPDMA_CH5_VDO</a>&#160;&#160;&#160;0X0720</td></tr>
<tr class="memdesc:a6725b830ddf92c80bb4edbe8cd3342c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH5_VDO.  <a href="#a6725b830ddf92c80bb4edbe8cd3342c6">More...</a><br/></td></tr>
<tr class="separator:a6725b830ddf92c80bb4edbe8cd3342c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae76b3085f778f3f571e00f8e5656bf0c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#ae76b3085f778f3f571e00f8e5656bf0c">XDPDMA_CH5_PYLD_SZ</a>&#160;&#160;&#160;0X0724</td></tr>
<tr class="memdesc:ae76b3085f778f3f571e00f8e5656bf0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH5_PYLD_SZ.  <a href="#ae76b3085f778f3f571e00f8e5656bf0c">More...</a><br/></td></tr>
<tr class="separator:ae76b3085f778f3f571e00f8e5656bf0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a19a86b7f534400b1346be9196898c82c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a19a86b7f534400b1346be9196898c82c">XDPDMA_CH5_DSCR_ID</a>&#160;&#160;&#160;0X0728</td></tr>
<tr class="memdesc:a19a86b7f534400b1346be9196898c82c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_CH5_DSCR_ID.  <a href="#a19a86b7f534400b1346be9196898c82c">More...</a><br/></td></tr>
<tr class="separator:a19a86b7f534400b1346be9196898c82c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a961ae58f3cbee2887e2b7cd410f736f0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a961ae58f3cbee2887e2b7cd410f736f0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_STRT_ADDRE_MSB_SHIFT</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:a961ae58f3cbee2887e2b7cd410f736f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac11f60d795266a619524a2add98f4c18"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac11f60d795266a619524a2add98f4c18"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_STRT_ADDRE_MSB_WIDTH</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:ac11f60d795266a619524a2add98f4c18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4360db5e3d1767af96d690e71db0b698"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4360db5e3d1767af96d690e71db0b698"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_STRT_ADDRE_MSB_MASK</b>&#160;&#160;&#160;0XFFFF</td></tr>
<tr class="separator:a4360db5e3d1767af96d690e71db0b698"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aad9612e7a83efa2dc263ca80d84ac24c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aad9612e7a83efa2dc263ca80d84ac24c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_STRT_ADDR_LSB_SHIFT</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:aad9612e7a83efa2dc263ca80d84ac24c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a256de48d0da074a4b95b8c9d81faa388"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a256de48d0da074a4b95b8c9d81faa388"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_STRT_ADDR_LSB_WIDTH</b>&#160;&#160;&#160;32</td></tr>
<tr class="separator:a256de48d0da074a4b95b8c9d81faa388"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a72c07eaf897a4b3e5fa4e6f0c5339122"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a72c07eaf897a4b3e5fa4e6f0c5339122"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_STRT_ADDR_LSB_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
<tr class="separator:a72c07eaf897a4b3e5fa4e6f0c5339122"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8db6d6f8aa0a0da08a94ade71cc6dbdd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8db6d6f8aa0a0da08a94ade71cc6dbdd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_NEXT_ADDRE_MSB_SHIFT</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:a8db6d6f8aa0a0da08a94ade71cc6dbdd"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_NEXT_ADDRE_MSB_WIDTH</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_NEXT_ADDRE_MSB_MASK</b>&#160;&#160;&#160;0XFFFF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_NEXT_ADDR_LSB_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_NEXT_ADDR_LSB_WIDTH</b>&#160;&#160;&#160;32</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_NEXT_ADDR_LSB_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_PYLD_CUR_ADDRE_MSB_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_PYLD_CUR_ADDRE_MSB_WIDTH</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_PYLD_CUR_ADDRE_MSB_MASK</b>&#160;&#160;&#160;0XFFFF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_PYLD_CUR_ADDR_LSB_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_PYLD_CUR_ADDR_LSB_WIDTH</b>&#160;&#160;&#160;32</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_PYLD_CUR_ADDR_LSB_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_DSCR_AXCACHE_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_DSCR_AXCACHE_WIDTH</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_DSCR_AXCACHE_MASK</b>&#160;&#160;&#160;0XF0000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_DSCR_AXPROT_SHIFT</b>&#160;&#160;&#160;14</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_DSCR_AXPROT_WIDTH</b>&#160;&#160;&#160;2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_DSCR_AXPROT_MASK</b>&#160;&#160;&#160;0XC000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_QOS_DATA_RD_SHIFT</b>&#160;&#160;&#160;10U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_QOS_DATA_RD_WIDTH</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_QOS_DATA_RD_MASK</b>&#160;&#160;&#160;0X3C00U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT</b>&#160;&#160;&#160;6U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_QOS_DSCR_RD_WIDTH</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_QOS_DSCR_RD_MASK</b>&#160;&#160;&#160;0X03C0U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_QOS_DSCR_WR_WIDTH</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_QOS_DSCR_WR_MASK</b>&#160;&#160;&#160;0X3CU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_PAUSE_SHIFT</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_PAUSE_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_PAUSE_MASK</b>&#160;&#160;&#160;0X2U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_EN_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_EN_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_CNTL_EN_MASK</b>&#160;&#160;&#160;0X1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_OTRAN_CNT_SHIFT</b>&#160;&#160;&#160;21</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_OTRAN_CNT_WIDTH</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_OTRAN_CNT_MASK</b>&#160;&#160;&#160;0X01E00000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_PREAMBLE_SHIFT</b>&#160;&#160;&#160;13</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_PREAMBLE_WIDTH</b>&#160;&#160;&#160;8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_PREAMBLE_MASK</b>&#160;&#160;&#160;0X1FE000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_EN_DSCR_INTR_SHIFT</b>&#160;&#160;&#160;12</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_EN_DSCR_INTR_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_EN_DSCR_INTR_MASK</b>&#160;&#160;&#160;0X1000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_EN_DSCR_UP_SHIFT</b>&#160;&#160;&#160;11</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_EN_DSCR_UP_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_EN_DSCR_UP_MASK</b>&#160;&#160;&#160;0X0800</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_DSCR_DONE_SHIFT</b>&#160;&#160;&#160;10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_DSCR_DONE_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_DSCR_DONE_MASK</b>&#160;&#160;&#160;0X0400</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_IGNR_DONE_SHIFT</b>&#160;&#160;&#160;9</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_IGNR_DONE_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_IGNR_DONE_MASK</b>&#160;&#160;&#160;0X0200</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_LDSCR_FRAME_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_LDSCR_FRAME_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_LDSCR_FRAME_MASK</b>&#160;&#160;&#160;0X0100</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_LAST_DSCR_SHIFT</b>&#160;&#160;&#160;7</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_LAST_DSCR_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_LAST_DSCR_MASK</b>&#160;&#160;&#160;0X80</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_EN_CRC_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_EN_CRC_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_EN_CRC_MASK</b>&#160;&#160;&#160;0X40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_MODE_SHIFT</b>&#160;&#160;&#160;5</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_MODE_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_MODE_MASK</b>&#160;&#160;&#160;0X20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_BURST_TYPE_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_BURST_TYPE_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_BURST_TYPE_MASK</b>&#160;&#160;&#160;0X10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_BURST_LEN_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_BURST_LEN_WIDTH</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_STATUS_BURST_LEN_MASK</b>&#160;&#160;&#160;0XF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_VDO_LINE_LENGTH_SHIFT</b>&#160;&#160;&#160;14</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_VDO_LINE_LENGTH_WIDTH</b>&#160;&#160;&#160;18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_VDO_LINE_LENGTH_MASK</b>&#160;&#160;&#160;0XFFFFC000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_VDO_STRIDE_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_VDO_STRIDE_WIDTH</b>&#160;&#160;&#160;14</td></tr>
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<tr class="memitem:adae0059e92236206aaf9ec426cea6d1e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="adae0059e92236206aaf9ec426cea6d1e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_VDO_STRIDE_MASK</b>&#160;&#160;&#160;0X3FFF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_PYLD_SZ_BYTE_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_PYLD_SZ_BYTE_WIDTH</b>&#160;&#160;&#160;32</td></tr>
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<tr class="memitem:aea8922d993f8e6e0a472470b594c5fbb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aea8922d993f8e6e0a472470b594c5fbb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_PYLD_SZ_BYTE_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_ID_VAL_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_ID_VAL_WIDTH</b>&#160;&#160;&#160;16</td></tr>
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<tr class="memitem:aeb0b8a25965cfea6ecaecdf91fb48334"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aeb0b8a25965cfea6ecaecdf91fb48334"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_CH_DSCR_ID_VAL_MASK</b>&#160;&#160;&#160;0XFFFF</td></tr>
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<tr class="memitem:a8e6abc6c84ac5fafca38a4aa994d46fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a8e6abc6c84ac5fafca38a4aa994d46fb">XDPDMA_ECO</a>&#160;&#160;&#160;0X0FFC</td></tr>
<tr class="memdesc:a8e6abc6c84ac5fafca38a4aa994d46fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XDPDMA_ECO.  <a href="#a8e6abc6c84ac5fafca38a4aa994d46fb">More...</a><br/></td></tr>
<tr class="separator:a8e6abc6c84ac5fafca38a4aa994d46fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7f004aad556b47b747a6d81efde7dba9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7f004aad556b47b747a6d81efde7dba9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ECO_VAL_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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<tr class="memitem:ad25c98a1fb06983350a77cd3f5edcc68"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad25c98a1fb06983350a77cd3f5edcc68"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ECO_VAL_WIDTH</b>&#160;&#160;&#160;32</td></tr>
<tr class="separator:ad25c98a1fb06983350a77cd3f5edcc68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab0fb824ab16067c6027c1baff87b22a0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab0fb824ab16067c6027c1baff87b22a0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_ECO_VAL_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
<tr class="separator:ab0fb824ab16067c6027c1baff87b22a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a35bc6de74ac7db2aa41d6e3c0a76ffed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdpdma__hw_8h.html#a35bc6de74ac7db2aa41d6e3c0a76ffed">XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a35bc6de74ac7db2aa41d6e3c0a76ffed"><td class="mdescLeft">&#160;</td><td class="mdescRight">DPDMA descriptor.  <a href="#a35bc6de74ac7db2aa41d6e3c0a76ffed">More...</a><br/></td></tr>
<tr class="separator:a35bc6de74ac7db2aa41d6e3c0a76ffed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a225b20e2626ef6842e5d0c2fd32f9a8f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a225b20e2626ef6842e5d0c2fd32f9a8f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_WIDTH</b>&#160;&#160;&#160;8</td></tr>
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<tr class="memitem:a4d38f586528f6f6ac2cfa5b0162f7e34"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4d38f586528f6f6ac2cfa5b0162f7e34"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_MASK</b>&#160;&#160;&#160;0XFF</td></tr>
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<tr class="memitem:a7206260c696cbef6b8caa6bae0ce3a9c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7206260c696cbef6b8caa6bae0ce3a9c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_EN_COMP_INTR_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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<tr class="memitem:a0288a36f4ce44ebb2ef40d0580dd61f6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0288a36f4ce44ebb2ef40d0580dd61f6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_EN_COMP_INTR_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:adee36ba745b190c96ae5675e40d609f5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="adee36ba745b190c96ae5675e40d609f5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_EN_COMP_INTR_MASK</b>&#160;&#160;&#160;0X0100</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_EN_DESC_UPDATE_SHIFT</b>&#160;&#160;&#160;9</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_EN_DESC_UPDATE_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_EN_DESC_UPDATE_MASK</b>&#160;&#160;&#160;0X0200</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_IGNORE_DONE_SHIFT</b>&#160;&#160;&#160;10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_IGNORE_DONE_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_IGNORE_DONE_MASK</b>&#160;&#160;&#160;0X0400</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_AXI_BURST_TYPE_SHIFT</b>&#160;&#160;&#160;11</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_AXI_BURST_TYPE_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_AXI_BURST_TYPE_MASK</b>&#160;&#160;&#160;0X0800</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_AXACACHE_SHIFT</b>&#160;&#160;&#160;12</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_AXACACHE_WIDTH</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_AXACACHE_MASK</b>&#160;&#160;&#160;0XF000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_AXPROT_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_AXPROT_WIDTH</b>&#160;&#160;&#160;2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_AXPROT_MASK</b>&#160;&#160;&#160;0X30000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_MODE_SHIFT</b>&#160;&#160;&#160;18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_MODE_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_MODE_MASK</b>&#160;&#160;&#160;0X40000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_SHIFT</b>&#160;&#160;&#160;19</td></tr>
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<tr class="memitem:a52bfdb6c617e447d2a75cd1d0b85642e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a52bfdb6c617e447d2a75cd1d0b85642e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_MASK</b>&#160;&#160;&#160;0X80000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_ENABLE_CRC_SHIFT</b>&#160;&#160;&#160;20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_ENABLE_CRC_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_ENABLE_CRC_MASK</b>&#160;&#160;&#160;0x00100000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_FRAME_SHIFT</b>&#160;&#160;&#160;21</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_FRAME_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_FRAME_MASK</b>&#160;&#160;&#160;0X200000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_DSCR_ID_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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<tr class="memitem:a58c30b2a04b787511ff3c08f6c4129f3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a58c30b2a04b787511ff3c08f6c4129f3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_DSCR_ID_WIDTH</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_DSCR_ID_MASK</b>&#160;&#160;&#160;0XFFFF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_XFER_SIZE_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_XFER_SIZE_WIDTH</b>&#160;&#160;&#160;32</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_XFER_SIZE_MASK</b>&#160;&#160;&#160;0x0000FFFF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_LINE_SIZE_HZ_RES_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_LINE_SIZE_HZ_RES_WIDTH</b>&#160;&#160;&#160;18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_LINE_SIZE_HZ_RES_MASK</b>&#160;&#160;&#160;0X3FFFF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT</b>&#160;&#160;&#160;18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_WIDTH</b>&#160;&#160;&#160;14</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_MASK</b>&#160;&#160;&#160;0XFFFC0000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_TS_LSB_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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<tr class="memitem:a6108fbba68143e7b064dbf5511dcd6a4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6108fbba68143e7b064dbf5511dcd6a4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_TS_LSB_WIDTH</b>&#160;&#160;&#160;32</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_TS_LSB_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_TS_MSB_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_TS_MSB_WIDTH</b>&#160;&#160;&#160;32</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_TS_MSB_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_TS_MSB_TS_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_TS_MSB_TS_WIDTH</b>&#160;&#160;&#160;9</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_TS_MSB_TS_MASK</b>&#160;&#160;&#160;0X01FF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_TS_MSB_STATUS_SHIFT</b>&#160;&#160;&#160;31</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_TS_MSB_STATUS_WIDTH</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_TS_MSB_STATUS_MASK</b>&#160;&#160;&#160;0X80000000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_WIDTH</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_MASK</b>&#160;&#160;&#160;0XFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT</b>&#160;&#160;&#160;16U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_WIDTH</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_MASK</b>&#160;&#160;&#160;0XFFFF0000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT23_2_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT23_2_WIDTH</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT23_2_MASK</b>&#160;&#160;&#160;0XFFFF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT23_3_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT23_3_WIDTH</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT23_3_MASK</b>&#160;&#160;&#160;0xFFFF0000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT45_4_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT45_4_WIDTH</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT45_4_MASK</b>&#160;&#160;&#160;0XFFFF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT45_5_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT45_5_WIDTH</b>&#160;&#160;&#160;16</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_ADDR_EXT45_5_MASK</b>&#160;&#160;&#160;0XFFFF0000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_NEXT_DESR_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_NEXT_DESR_WIDTH</b>&#160;&#160;&#160;32</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_NEXT_DESR_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR_WIDTH</b>&#160;&#160;&#160;32U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR2_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR2_WIDTH</b>&#160;&#160;&#160;32</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR2_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR3_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR3_WIDTH</b>&#160;&#160;&#160;32</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR3_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR4_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR4_WIDTH</b>&#160;&#160;&#160;32</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR4_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR5_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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<tr class="memitem:a5eeb7c51c27b5299ed0f00e01982f485"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5eeb7c51c27b5299ed0f00e01982f485"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR5_WIDTH</b>&#160;&#160;&#160;32</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_DESCRIPTOR_SRC_ADDR5_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_TRIGGER_EN</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_RETRIGGER_EN</b>&#160;&#160;&#160;2U</td></tr>
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<tr class="memitem:ad0dcdf5dad5e8c0357e17e168d5084d1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad0dcdf5dad5e8c0357e17e168d5084d1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_TRIGGER_DONE</b>&#160;&#160;&#160;0U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPDMA_RETRIGGER_DONE</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:a915930cf195b15087472c5c665c31dac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register access macro definitions.</div></td></tr>
<tr class="memitem:aabb8044fa4e716eef0d6d7327c47e721"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aabb8044fa4e716eef0d6d7327c47e721"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDpDma_In32</b>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="separator:aabb8044fa4e716eef0d6d7327c47e721"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a69e5cb26a66517fa14270cf48ee9cf26"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a69e5cb26a66517fa14270cf48ee9cf26"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDpDma_Out32</b>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="separator:a69e5cb26a66517fa14270cf48ee9cf26"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a92edcf2bfb1c790b8168ebdca1297987"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH0_CNTL&#160;&#160;&#160;0X0218U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH0_CNTL. </p>

<p>Referenced by <a class="el" href="xdpdma_8c.html#ac04dd8bf90f181c5ca44af2b0bd1e3d2">XDpDma_SetQOS()</a>.</p>

</div>
</div>
<a class="anchor" id="a09b2ae341d14ddfa549e8ab3834c3196"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH0_DSCR_ID&#160;&#160;&#160;0X0228</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH0_DSCR_ID. </p>

</div>
</div>
<a class="anchor" id="afc59a959d6b0550dcdc267e735f33cb6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH0_DSCR_NEXT_ADDR&#160;&#160;&#160;0X020C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH0_DSCR_NEXT_ADDR. </p>

</div>
</div>
<a class="anchor" id="adcc6ad043d68513eb376091718cafafe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH0_DSCR_NEXT_ADDRE&#160;&#160;&#160;0X0208</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH0_DSCR_NEXT_ADDRE. </p>

</div>
</div>
<a class="anchor" id="abd78f71b01f8530af95fb64f69d876ea"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH0_DSCR_STRT_ADDR&#160;&#160;&#160;0X0204U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH0_DSCR_STRT_ADDR. </p>

</div>
</div>
<a class="anchor" id="a991f6234e0556e6e723eb66f35a6f082"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH0_DSCR_STRT_ADDRE&#160;&#160;&#160;0X0200U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH0_DSCR_STRT_ADDRE. </p>

</div>
</div>
<a class="anchor" id="a07c70571b263fbff92b84d1ecb98f1bf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH0_PYLD_CUR_ADDR&#160;&#160;&#160;0X0214</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH0_PYLD_CUR_ADDR. </p>

</div>
</div>
<a class="anchor" id="ae4f4baee2a66dc28a10f8f83a5dfd861"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH0_PYLD_CUR_ADDRE&#160;&#160;&#160;0X0210</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH0_PYLD_CUR_ADDRE. </p>

</div>
</div>
<a class="anchor" id="a1a468a7a272cfb638c4e439a93329aca"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH0_PYLD_SZ&#160;&#160;&#160;0X0224</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH0_PYLD_SZ. </p>

</div>
</div>
<a class="anchor" id="a83f42b898372fe67e0bb5d7919cdcac6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH0_STATUS&#160;&#160;&#160;0X021CU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH0_STATUS. </p>

</div>
</div>
<a class="anchor" id="ae09303aba43f8418f295f0ff4dd34f92"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH0_VDO&#160;&#160;&#160;0X0220</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH0_VDO. </p>

</div>
</div>
<a class="anchor" id="adf0241f99ad07d09a66557be911d0975"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH1_CNTL&#160;&#160;&#160;0X0318</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH1_CNTL. </p>

</div>
</div>
<a class="anchor" id="a51be3073d3032a7ae655e3e588785a15"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH1_DSCR_ID&#160;&#160;&#160;0X0328</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH1_DSCR_ID. </p>

</div>
</div>
<a class="anchor" id="ae8e52410cadfe52524a23147ec6c1b44"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH1_DSCR_NEXT_ADDR&#160;&#160;&#160;0X030C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH1_DSCR_NEXT_ADDR. </p>

</div>
</div>
<a class="anchor" id="a0b06d219911219117b2395959ebb8ba0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH1_DSCR_NEXT_ADDRE&#160;&#160;&#160;0X0308</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH1_DSCR_NEXT_ADDRE. </p>

</div>
</div>
<a class="anchor" id="a6fa9a18f33a9772a8a580933d7b03a73"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH1_DSCR_STRT_ADDR&#160;&#160;&#160;0X0304</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH1_DSCR_STRT_ADDR. </p>

</div>
</div>
<a class="anchor" id="a838a5495033542c257ca35b82c2aa477"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH1_DSCR_STRT_ADDRE&#160;&#160;&#160;0X0300</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH1_DSCR_STRT_ADDRE. </p>

</div>
</div>
<a class="anchor" id="aa3c7d69760787868b85d2d8f75a44243"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH1_PYLD_CUR_ADDR&#160;&#160;&#160;0X0314</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH1_PYLD_CUR_ADDR. </p>

</div>
</div>
<a class="anchor" id="aabab7a547102c88990ed3d99aa8b80e9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH1_PYLD_CUR_ADDRE&#160;&#160;&#160;0X0310</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH1_PYLD_CUR_ADDRE. </p>

</div>
</div>
<a class="anchor" id="a180f50f97fb4e14435b35fe63d61ac64"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH1_PYLD_SZ&#160;&#160;&#160;0X0324</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH1_PYLD_SZ. </p>

</div>
</div>
<a class="anchor" id="a54adbe2e6805c17f5e7d1b5cc15692a7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH1_STATUS&#160;&#160;&#160;0X031C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH1_STATUS. </p>

</div>
</div>
<a class="anchor" id="af24fb66e7b209f835184289ae36ee36a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH1_VDO&#160;&#160;&#160;0X0320</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH1_VDO. </p>

</div>
</div>
<a class="anchor" id="ad79048ee00c1ac857520a93996e260a8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH2_CNTL&#160;&#160;&#160;0X0418</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH2_CNTL. </p>

</div>
</div>
<a class="anchor" id="a3424199190b4c20992d7a3683262d6ba"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH2_DSCR_ID&#160;&#160;&#160;0X0428</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH2_DSCR_ID. </p>

</div>
</div>
<a class="anchor" id="a24eeab5d6028cf73cf27ce4e1a32406b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH2_DSCR_NEXT_ADDR&#160;&#160;&#160;0X040C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH2_DSCR_NEXT_ADDR. </p>

</div>
</div>
<a class="anchor" id="a27cba17fb4ca046bccf321dcaed13738"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH2_DSCR_NEXT_ADDRE&#160;&#160;&#160;0X0408</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH2_DSCR_NEXT_ADDRE. </p>

</div>
</div>
<a class="anchor" id="a1e9c5e509ee56fd597ca21f83e7594cd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH2_DSCR_STRT_ADDR&#160;&#160;&#160;0X0404</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH2_DSCR_STRT_ADDR. </p>

</div>
</div>
<a class="anchor" id="a07c328da361c190edfe49c699a295779"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH2_DSCR_STRT_ADDRE&#160;&#160;&#160;0X0400</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH2_DSCR_STRT_ADDRE. </p>

</div>
</div>
<a class="anchor" id="a9c43476d38eee3524660904391b7301e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH2_PYLD_CUR_ADDR&#160;&#160;&#160;0X0414</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH2_PYLD_CUR_ADDR. </p>

</div>
</div>
<a class="anchor" id="a7930ea87af739ba87dcec63e2a5069f4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH2_PYLD_CUR_ADDRE&#160;&#160;&#160;0X0410</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH2_PYLD_CUR_ADDRE. </p>

</div>
</div>
<a class="anchor" id="a9464a8b39bf0218f962263d8d8165a12"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH2_PYLD_SZ&#160;&#160;&#160;0X0424</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH2_PYLD_SZ. </p>

</div>
</div>
<a class="anchor" id="a174208187f3bd59b987baed4aebaa88e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH2_STATUS&#160;&#160;&#160;0X041C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH2_STATUS. </p>

</div>
</div>
<a class="anchor" id="a2420134029f56c26ff3c8f84adf39fd3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH2_VDO&#160;&#160;&#160;0X0420</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH2_VDO. </p>

</div>
</div>
<a class="anchor" id="a0f51ff98221cebff1c2b490c072bb61f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH3_CNTL&#160;&#160;&#160;0X0518</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH3_CNTL. </p>

</div>
</div>
<a class="anchor" id="aa89a23e17f5dca705dd19bd809734c1c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH3_DSCR_ID&#160;&#160;&#160;0X0528</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH3_DSCR_ID. </p>

</div>
</div>
<a class="anchor" id="a977cdb3d4313659354009810f7277a62"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH3_DSCR_NEXT_ADDR&#160;&#160;&#160;0X050C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH3_DSCR_NEXT_ADDR. </p>

</div>
</div>
<a class="anchor" id="a74a3b5246ce91732eec1cdd303fec4d9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH3_DSCR_NEXT_ADDRE&#160;&#160;&#160;0X0508</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH3_DSCR_NEXT_ADDRE. </p>

</div>
</div>
<a class="anchor" id="a6de8f7d3387d33d28355c72232dfb2f2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH3_DSCR_STRT_ADDR&#160;&#160;&#160;0X0504</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH3_DSCR_STRT_ADDR. </p>

</div>
</div>
<a class="anchor" id="a899cf6d0537238921a4feb690a9f2f69"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH3_DSCR_STRT_ADDRE&#160;&#160;&#160;0X0500</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH3_DSCR_STRT_ADDRE. </p>

</div>
</div>
<a class="anchor" id="a49ae885b83aabf0eb3d6e49e1be1904e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH3_PYLD_CUR_ADDR&#160;&#160;&#160;0X0514</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH3_PYLD_CUR_ADDR. </p>

</div>
</div>
<a class="anchor" id="aa57ee9cb549632fcc9ab768ba58e6121"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH3_PYLD_CUR_ADDRE&#160;&#160;&#160;0X0510</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH3_PYLD_CUR_ADDRE. </p>

</div>
</div>
<a class="anchor" id="a2054066aaea2ba768171aa54d7c715d9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH3_PYLD_SZ&#160;&#160;&#160;0X0524</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH3_PYLD_SZ. </p>

</div>
</div>
<a class="anchor" id="a28e9952949e1b86e1fe64b480221ba8b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH3_STATUS&#160;&#160;&#160;0X051C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH3_STATUS. </p>

</div>
</div>
<a class="anchor" id="ab0639641282a93a5614e6d1c2c0d932a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH3_VDO&#160;&#160;&#160;0X0520</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH3_VDO. </p>

</div>
</div>
<a class="anchor" id="a477f10fb1961935108d8cc9d13483209"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH4_CNTL&#160;&#160;&#160;0X0618</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH4_CNTL. </p>

</div>
</div>
<a class="anchor" id="a7423c58a9102a77da3934aa0bd599660"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH4_DSCR_ID&#160;&#160;&#160;0X0628</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH4_DSCR_ID. </p>

</div>
</div>
<a class="anchor" id="a4930f1be4260d774052c6436e24d6d64"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH4_DSCR_NEXT_ADDR&#160;&#160;&#160;0X060C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH4_DSCR_NEXT_ADDR. </p>

</div>
</div>
<a class="anchor" id="abb7642899e2f3020e8b1e16c96ca7ceb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH4_DSCR_NEXT_ADDRE&#160;&#160;&#160;0X0608</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH4_DSCR_NEXT_ADDRE. </p>

</div>
</div>
<a class="anchor" id="ad443ff9b10e6977908eaa2634c9aa538"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH4_DSCR_STRT_ADDR&#160;&#160;&#160;0X0604</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH4_DSCR_STRT_ADDR. </p>

</div>
</div>
<a class="anchor" id="a66b3c1a5524bea5746e3710f785a25c2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH4_DSCR_STRT_ADDRE&#160;&#160;&#160;0X0600</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH4_DSCR_STRT_ADDRE. </p>

</div>
</div>
<a class="anchor" id="ad60588b1e6b47e841dd36dae71978a07"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH4_PYLD_CUR_ADDR&#160;&#160;&#160;0X0614</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH4_PYLD_CUR_ADDR. </p>

</div>
</div>
<a class="anchor" id="ae98fd97a3b1ca8c2ccd0cbe4d2abae17"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH4_PYLD_CUR_ADDRE&#160;&#160;&#160;0X0610</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH4_PYLD_CUR_ADDRE. </p>

</div>
</div>
<a class="anchor" id="a184c60737fe7e22521b4e1ab74aed5e6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH4_PYLD_SZ&#160;&#160;&#160;0X0624</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH4_PYLD_SZ. </p>

</div>
</div>
<a class="anchor" id="afda009aaa74723d26c6ad2ca57f2028c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH4_STATUS&#160;&#160;&#160;0X061C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH4_STATUS. </p>

</div>
</div>
<a class="anchor" id="a755b2d11cabc3a67143464e5ba68854b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH4_VDO&#160;&#160;&#160;0X0620</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH4_VDO. </p>

</div>
</div>
<a class="anchor" id="a8a40bc00f2c620de3dc434bebaf4e1ed"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH5_CNTL&#160;&#160;&#160;0X0718</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH5_CNTL. </p>

</div>
</div>
<a class="anchor" id="a19a86b7f534400b1346be9196898c82c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH5_DSCR_ID&#160;&#160;&#160;0X0728</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH5_DSCR_ID. </p>

</div>
</div>
<a class="anchor" id="ab779b463c7a0e3acb425deff37219a17"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH5_DSCR_NEXT_ADDR&#160;&#160;&#160;0X070C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH5_DSCR_NEXT_ADDR. </p>

</div>
</div>
<a class="anchor" id="a1a42f34bdc393cf3492f578c5d996263"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH5_DSCR_NEXT_ADDRE&#160;&#160;&#160;0X0708</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH5_DSCR_NEXT_ADDRE. </p>

</div>
</div>
<a class="anchor" id="af9597e4aec3ced8b5e3a6d45485ee861"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH5_DSCR_STRT_ADDR&#160;&#160;&#160;0X0704</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH5_DSCR_STRT_ADDR. </p>

</div>
</div>
<a class="anchor" id="a4c5206b6dce1a65a1e6db4114621c5fc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH5_DSCR_STRT_ADDRE&#160;&#160;&#160;0X0700</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH5_DSCR_STRT_ADDRE. </p>

</div>
</div>
<a class="anchor" id="a397cac23ead0877eb96b859078d88ab0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH5_PYLD_CUR_ADDR&#160;&#160;&#160;0X0714</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH5_PYLD_CUR_ADDR. </p>

</div>
</div>
<a class="anchor" id="aadf8c4c53a62f5cc7c39f353d3ca1e0a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH5_PYLD_CUR_ADDRE&#160;&#160;&#160;0X0710</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH5_PYLD_CUR_ADDRE. </p>

</div>
</div>
<a class="anchor" id="ae76b3085f778f3f571e00f8e5656bf0c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH5_PYLD_SZ&#160;&#160;&#160;0X0724</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH5_PYLD_SZ. </p>

</div>
</div>
<a class="anchor" id="ab76a5988722598d68ab200d4e0c1b940"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH5_STATUS&#160;&#160;&#160;0X071C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH5_STATUS. </p>

</div>
</div>
<a class="anchor" id="a6725b830ddf92c80bb4edbe8cd3342c6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CH5_VDO&#160;&#160;&#160;0X0720</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CH5_VDO. </p>

</div>
</div>
<a class="anchor" id="a8ef7259c3e780171f2e405484ee4fec3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_CNTL&#160;&#160;&#160;0X0100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_CNTL. </p>

</div>
</div>
<a class="anchor" id="a35bc6de74ac7db2aa41d6e3c0a76ffed"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DPDMA descriptor. </p>

</div>
</div>
<a class="anchor" id="a8e6abc6c84ac5fafca38a4aa994d46fb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_ECO&#160;&#160;&#160;0X0FFC</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_ECO. </p>

</div>
</div>
<a class="anchor" id="add4abc05f7be2300a456fdfb4e86f109"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_EIDS&#160;&#160;&#160;0X0020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_EIDS. </p>

</div>
</div>
<a class="anchor" id="ac74c27e37b98e661231ed17c7346cb91"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_EIEN&#160;&#160;&#160;0X001C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_EIEN. </p>

</div>
</div>
<a class="anchor" id="a584f0fe1ed788d81e9add223ae89ce3c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_EIMR&#160;&#160;&#160;0X0018</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_EIMR. </p>

</div>
</div>
<a class="anchor" id="a4acf94c528731ceeede26f6d192d014c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_EISR&#160;&#160;&#160;0X0014</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_EISR. </p>

</div>
</div>
<a class="anchor" id="a7e16e6689ff8b9c514eb8908baf79bc2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_ERR_CTRL&#160;&#160;&#160;0X0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_ERR_CTRL. </p>

</div>
</div>
<a class="anchor" id="acd9b1930d59d62b2de10bcebfe383b5e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_GBL&#160;&#160;&#160;0X0104U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_GBL. </p>

<p>Referenced by <a class="el" href="xdpdma_8c.html#a33d14a186926a53012087f81a4fd3f16">XDpDma_ReTrigger()</a>, and <a class="el" href="xdpdma_8c.html#aa031afe32833d3c31cf50c1245d6a5a3">XDpDma_Trigger()</a>.</p>

</div>
</div>
<a class="anchor" id="a2849f3b0fe6751abc24db3fea5796e4d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_IDS&#160;&#160;&#160;0X0010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_IDS. </p>

</div>
</div>
<a class="anchor" id="a7bd98cc3f3b3d8929288e48f73f9fe6d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_IEN&#160;&#160;&#160;0X000CU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_IEN. </p>

<p>Referenced by <a class="el" href="xdpdma__intr_8c.html#a1789f821f2b216d7693514352b300216">XDpDma_InterruptEnable()</a>.</p>

</div>
</div>
<a class="anchor" id="a92d0fcfcd996d69e3ce0a2e70816f54a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_IMR&#160;&#160;&#160;0X0008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_IMR. </p>

</div>
</div>
<a class="anchor" id="ace9e0daf87e3d7d42ac516869d89d444"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPDMA_ISR&#160;&#160;&#160;0X0004U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register: XDPDMA_ISR. </p>

<p>Referenced by <a class="el" href="xdpdma__intr_8c.html#a856c484c8e45df996ba6aa97f38392dd">XDpDma_InterruptHandler()</a>, and <a class="el" href="xdpdma__intr_8c.html#aecdf54c8a3174a7547021952de639875">XDpDma_VSyncHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a6740ca444093c5883a293e6282d79ec7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDpDma_ReadModifyWrite</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Mask&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xdpdma__hw_8h.html#a836430cbab9cc5f0fae3b5f2b54daca6">XDpDma_WriteReg</a>((BaseAddress), (RegOffset), \</div>
<div class="line">                                ((<a class="code" href="xdpdma__hw_8h.html#a05137b71ce7a978700ba5c362704a646">XDpDma_ReadReg</a>(BaseAddress, RegOffset) &amp;  \</div>
<div class="line">                                 ~(Mask)) | Data))</div>
<div class="ttc" id="xdpdma__hw_8h_html_a05137b71ce7a978700ba5c362704a646"><div class="ttname"><a href="xdpdma__hw_8h.html#a05137b71ce7a978700ba5c362704a646">XDpDma_ReadReg</a></div><div class="ttdeci">#define XDpDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This is a low-level function that reads from the specified register. </div><div class="ttdef"><b>Definition:</b> xdpdma_hw.h:1738</div></div>
<div class="ttc" id="xdpdma__hw_8h_html_a836430cbab9cc5f0fae3b5f2b54daca6"><div class="ttname"><a href="xdpdma__hw_8h.html#a836430cbab9cc5f0fae3b5f2b54daca6">XDpDma_WriteReg</a></div><div class="ttdeci">#define XDpDma_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This is a low-level function that writes to the specified register. </div><div class="ttdef"><b>Definition:</b> xdpdma_hw.h:1755</div></div>
</div><!-- fragment -->
<p>This is a low-level function that writes to the specified register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to write to. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit data to write to the specified register. </td></tr>
    <tr><td class="paramname">Mask</td><td>is the 32-bit field to which data is to be written</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XDpDma_ReadModifyWrite(u32 BaseAddress, u32 RegOffset, u32 Data) </dd></dl>

<p>Referenced by <a class="el" href="xdpdma_8c.html#ac04dd8bf90f181c5ca44af2b0bd1e3d2">XDpDma_SetQOS()</a>.</p>

</div>
</div>
<a class="anchor" id="a05137b71ce7a978700ba5c362704a646"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDpDma_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XDpDma_In32((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This is a low-level function that reads from the specified register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be read from.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the specified register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 XDpDma_ReadReg(u32 BaseAddress, u32 RegOffset </dd></dl>

<p>Referenced by <a class="el" href="xdpdma__intr_8c.html#a856c484c8e45df996ba6aa97f38392dd">XDpDma_InterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a836430cbab9cc5f0fae3b5f2b54daca6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDpDma_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XDpDma_Out32((BaseAddress) + (RegOffset), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This is a low-level function that writes to the specified register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to write to. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit data to write to the specified register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xdpdma__hw_8h.html#a836430cbab9cc5f0fae3b5f2b54daca6" title="This is a low-level function that writes to the specified register. ">XDpDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="xdpdma__intr_8c.html#a1789f821f2b216d7693514352b300216">XDpDma_InterruptEnable()</a>, <a class="el" href="xdpdma__intr_8c.html#a856c484c8e45df996ba6aa97f38392dd">XDpDma_InterruptHandler()</a>, <a class="el" href="xdpdma_8c.html#a33d14a186926a53012087f81a4fd3f16">XDpDma_ReTrigger()</a>, <a class="el" href="xdpdma_8c.html#aa031afe32833d3c31cf50c1245d6a5a3">XDpDma_Trigger()</a>, and <a class="el" href="xdpdma__intr_8c.html#aecdf54c8a3174a7547021952de639875">XDpDma_VSyncHandler()</a>.</p>

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